# US 11,309,416 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,416 B2 - Document ID: US11309416B2 - Status: Granted - Kind: B2 - Application number: 16/757,766 - Filed: 2017-12-21 - Published: 2020-09-17 - Granted: 2022-04-19 - Earliest claimed: 2017-12-21 - Assignees: Mitsubishi Electric Corporation - Applicants: Mitsubishi Electric Corporation - Inventors: Hideyuki Hatta; Shiro Hino; Katsutoshi Sugawara - Web page: https://patentgrep.com/patent/US11309416B2 ## CPC - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 12/00: Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT] - H10D 12/031: {of IGBTs} - H10D 12/032: {of vertical IGBTs} - H10D 12/441: {Vertical IGBTs} - H10D 30/0291: {of vertical DMOS [VDMOS] FETs} - H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes} - H10D 30/635: {having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs} - H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)} - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10D 62/145: {Emitter regions of IGBTs} - H10D 62/149: {Source or drain regions of field-effect devices} - H10D 62/153: {Impurity concentrations or distributions} - H10D 62/154: {Dispositions} - H10D 62/155: {Shapes (cell layout of DMOS H10D62/127)} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D 62/8325: {Silicon carbide} - H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates} - H10D 84/141: {VDMOS having built-in components} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A drift layer has a first conductivity type. A well region has a second conductivity type. A well contact region has a resistivity lower than that of the well region. A source contact region is provided on the well region, separated from the drift layer by the well region, and has the first conductivity type. A source resistance region is provided on the well region, separated from the drift layer by the well region, is adjacent to the source contact region, has the first conductivity type, and has a sheet resistance higher than that of the source contact region. A source electrode contacts the source contact region, the well contact region, and the source resistance region, and is continuous with the channel at least through the source resistance region. ## Claims ### Claim 1 A semiconductor device having a channel, the semiconductor device comprising: a semiconductor substrate having a first main surface and a second main surface on the opposite side of the first main surface, and having an in-plane direction parallel to the second main surface; a drain electrode provided on the first main surface of the semiconductor substrate; a drift layer provided on the second main surface of the semiconductor substrate and having a first conductivity type; a well region provided on the drift layer, having a second conductivity type different from the first conductivity type, and having a part forming the channel of the semiconductor device; a well contact region provided on the well region, having the second conductivity type, and having a resistivity lower than that of the well region; a source contact region provided on the well region, separated from the drift layer by the well region, and having the first conductivity type; a source resistance region provided on the well region, separated from the drift layer by the well region, adjacent to the source contact region in the in-plane direction, having the first conductivity type, and having a sheet resistance higher than that of the source contact region; a gate insulating film covering the channel of the well region; a gate electrode provided on the gate insulating film; and a source electrode contacting the source contact region and the well contact region, and continuous with the channel at least through the source resistance region, the source electrode directly contacting the source resistance region. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor device comprises an insulating layer including the gate insulating film, the insulating layer is provided with a contact hole in which the source electrode is buried, and the contact hole has an outer periphery crossing the source resistance region. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the channel extends in the in-plane direction. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein a trench having a side wall penetrating the well region to reach the drift layer is provided, and the channel is arranged on the side wall. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, further comprising: a trench bottom protective region provided at the bottom of the trench and having the second conductivity type; and a trench side wall protective region provided on a part of the side wall of the trench, contacting the trench bottom protective region and the well region, and having the second conductivity type. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein at least a part of the trench side wall protective region is arranged to be adjacent to or overlap the well contact region in a plan view. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, further comprising: a source extension region adjacent to the source resistance region, separated from the source contact region, separated from the drift layer by the well region, and having the first conductivity type, wherein the source resistance region is continuous with the channel through the source extension region. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein each of the source resistance region and the well contact region is arranged between the source contact region and the source extension region in the in-plane direction. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein the source resistance region is adjacent to the well contact region in the in-plane direction. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein the source resistance region includes a first part arranged on the well region and a second part arranged on the first part, and the first part has a resistivity lower than that of the second part. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein the well contact region is arranged in such a manner as not to have a part contacting the gate electrode with only the gate insulating film interposed therebetween. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, wherein a contact resistance between the source electrode and the source resistance region is ten times larger or more than a contact resistance between the source electrode and the source contact region. ### Claim 13 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor device has a plurality of unit cells arranged in a stripe shape, the well contact region has parts opposite to each other across the source contact region in a direction crossing a direction in which the stripe shape extends, and the centers of the opposite parts are shifted from each other in the direction in which the stripe shape extends. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor substrate, the drift layer, and the well region are made of silicon carbide. ### Claim 15 (depends on 1) The semiconductor device according to claim 1, wherein the source resistance region is adjacent to the well contact region in the in-plane direction.