# US 11,309,414 B2 · Metal oxide semiconductor (MOS) controlled devices and methods of making the same

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- Number: US 11,309,414 B2
- Document ID: US11309414B2
- Status: Granted
- Kind: B2
- Application number: 16/783,754
- Filed: 2020-02-06
- Published: 2020-06-04
- Granted: 2022-04-19
- Earliest claimed: 2017-06-29
- Assignees: Monolith Semiconductor Inc.
- Applicants: Monolith Semiconductor Inc.
- Inventors: Kevin Matocha; Sauvik Chowdhury; Kiran Chatty; John Nowak
- Web page: https://patentgrep.com/patent/US11309414B2

## CPC

- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 12/031: {of IGBTs}
- H10D 12/441: {Vertical IGBTs}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/125: {Shapes of junctions between the regions}
- H10D 62/133: {Emitter regions of BJTs}
- H10D 62/153: {Impurity concentrations or distributions}
- H10D 62/154: {Dispositions}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/8325: {Silicon carbide}
- H10D 62/834: further characterised by the dopants
- H10D 64/01366: {the semiconductor being silicon carbide}
- H10D 64/232: {Emitter electrodes for IGBTs}
- H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies}
- H10D 64/516: {the thicknesses being non-uniform}
- H10P 14/6308: {of Group IV semiconductors}
- H10P 14/6322: {Formation by thermal treatments (formation by plasma treatment H10P14/6319)}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/2042: {into crystalline silicon carbide}
- H10P 30/208: {of electrically inactive species}
- H10P 30/21: {of electrically active species}
- H10P 30/218: {characterised by the implantation in a compound semiconductor of both electrically active and inactive species in the same semiconductor region to be doped n-type or p-type}
- H10D 12/032: {of vertical IGBTs}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Metal-Oxide-Semiconductor (MOS) controlled semiconductor devices and methods of making the devices are provided. The devices include a gate which controls current flow through channel regions positioned between source/emitter and drain regions of the device. The devices include a gate oxide layer having a variable thickness. The thickness of the gate oxide layer under the edge of the gate and over the source/emitter regions is different than the thickness over the channel regions of the device. The oxide layer thickness near the edge of the gate can be greater than the oxide layer thickness over the channel regions. The source/emitter regions can be implanted to provide enhanced oxide growth during gate oxide formation. The source/emitter region can include regions that are implanted to provide enhanced oxide growth during gate oxide formation and regions which do not provide enhanced oxide growth during gate oxide formation. The devices can be SiC devices such as SiC MOSFETs and SiC IGBTs.

## Claims

### Claim 1

A method of making a semiconductor device having an oxide layer of varying thickness, the method comprising:
providing a silicon carbide (SiC) layer;
providing a P-well extending from an upper surface of the SiC layer; forming a first n-type region in a surface of the P-well;
forming a second n-type region within the first n-type region, and within the P-well, wherein the second n-type region comprises a higher concentration of n-type dopants than the first n-type region, wherein the first n-type region, the second n-type region, and the P-well extend to the upper surface; and
forming an oxide (SiO2) layer on the upper surface by thermally oxidizing the SiC layer, wherein the SiO2 layer is formed on the first n-type region and the second n-type region until a difference between a first average thickness of the SiO2 layer in the first n-type region and a second average thickness the SiO2 layer in the second n-type region is at least 25%.

### Claim 2 (depends on 1)

The method of claim 1, wherein the SiO2 layer is formed until: the first average thickness is different than the second average thickness by at least 50%; the first average thickness is different than the second average thickness by at least 100%; the first average thickness is different than the second average thickness by at least 200%; or the first average thickness is different than the second average thickness by at least 300%.

### Claim 3 (depends on 1)

The method of claim 1, wherein the SiC layer is a drift layer, disposed on a SiC substrate, wherein the p-well defines a channel region between the first n-type region and the drift layer at the upper surface.

### Claim 4 (depends on 3)

The method of claim 3, further comprising: forming a gate electrode on the SiO2 layer, wherein the gate electrode layer extends over the drift layer, the channel region, an outer portion of the first n-type region, adjacent the channel region, and an outer portion of the second n-type region, adjacent the outer portion of the first n-type region.

### Claim 5 (depends on 4)

The method of claim 4, wherein the SiO2 layer extends below the upper surface.

### Claim 6 (depends on 4)

The method of claim 4, wherein the SiO2 layer comprises a gate oxide layer, wherein a boundary between a thicker portion of the gate oxide layer and a thinner portion of the gate oxide layer is spaced apart from the channel region by the first n-type region.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first n-type region is formed by implanting an n-type species at a dose of 2×1014 cm−2 to 9×1014 cm−2.

### Claim 8 (depends on 7)

The method of claim 7, wherein the first implant species comprises nitrogen, phosphorus or a combination thereof.

### Claim 9 (depends on 1)

The method of claim 1, wherein the second n-type region is formed by implanting an n-type species at a dose of 1×1015 cm−2 to 1×1016 cm−2.

### Claim 10 (depends on 9)

The method of claim 9, wherein the second implant species comprises nitrogen, phosphorus, or a combination thereof.

### Claim 11 (depends on 1)

The method of claim 1, wherein: the first n-type region is formed in the p-well using a self-aligned process; and/or the second n-type region is formed in the first n-type region using a self-aligned process.

### Claim 12 (depends on 1)

The method of claim 1, wherein the first n-type region and the second n-type region are elongate regions extending in an x direction in the drift layer and having edges in a y-direction perpendicular to the x-direction, wherein edges of the second n-type region are spaced from edges of the first n-type region in the y-direction by 0.1 μm to 0.5 μm.

### Claim 13 (depends on 1)

The method of claim 1 wherein the second n-type region comprises a higher level of implant damage than the first n-type region.

### Claim 14 (depends on 1)

The method of claim 1 wherein the first n-type region is formed using at least a first implant species, and wherein the second n-type region is formed using at least a second implant species, different than the first implant species.

### Claim 15

A method of making a semiconductor device having an oxide layer of varying thickness, the method comprising:
providing a silicon carbide (SiC) layer;
providing a P-well extending from an upper surface of the SiC layer;
forming a first n-type region in a surface of the P-well;
forming a second n-type region within the first n-type region, and within the P-well, wherein the second n-type region comprises a higher level of implant damage than the first n-type region, wherein the first n-type region, the second n-type region, and the P-well extend to the upper surface; and forming an oxide (SiO2) layer on the upper surface by thermally oxidizing the SiC layer, wherein the SiO2 layer is formed on the first n-type region and the second n-type region until a difference between a first average thickness of the SiO2 layer in the first n-type region and a second average thickness the SiO2 layer in the second n-type region is at least 25%.

### Claim 16 (depends on 15)

The method of claim 15, wherein the first n-type region is formed by implanting at least a first implant species, wherein the first implant species comprises nitrogen, phosphorus or a combination thereof, and wherein the second n-type region is formed by implanting at least a second implant species, wherein the second implant species comprises nitrogen, phosphorus, silicon, carbon, argon, neon or a combination thereof.

### Claim 17

A method of making a semiconductor device having an oxide layer of varying thickness, the method comprising:
providing a silicon carbide (SiC) layer; providing a P-well extending from an upper surface of the SiC layer;
forming a first n-type region in a surface of a P-well using at least a first implant species;
forming a second n-type region within the first n-type region, and within the P-well, wherein the second n-type region is formed using at least a second implant species, different than the first implant species, wherein the first n-type region, the second n-type region, and the P-well extend to the upper surface; and
forming an oxide (SiO2) layer on the upper surface by thermally oxidizing the SiC layer, wherein the SiO2 layer is formed on the first n-type region and the second n-type region until a difference between a first average thickness of the SiO2 layer in the first n-type region and a second average thickness the SiO2 layer in the second n-type region is at least 25%.

### Claim 18 (depends on 17)

The method of claim 17, wherein the first implant species comprises at least one of: nitrogen and phosphorus, and wherein the second n-type dopant comprises at least one of: nitrogen, phosphorus, silicon, carbon, argon, and neon.