# US 11,309,413 B2 · Semiconductor device with improved short circuit withstand time and methods for manufacturing the same

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- Number: US 11,309,413 B2
- Document ID: US11309413B2
- Status: Granted
- Kind: B2
- Application number: 16/598,646
- Filed: 2019-10-10
- Published: 2021-04-15
- Granted: 2022-04-19
- Earliest claimed: 2019-10-10
- Assignees: Wolfspeed, Inc.
- Applicants: Wolfspeed, Inc.
- Inventors: Sei-Hyung Ryu
- Web page: https://patentgrep.com/patent/US11309413B2

## CPC

- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 12/031: {of IGBTs}
- H10D 12/032: {of vertical IGBTs}
- H10D 12/441: {Vertical IGBTs}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 62/152: {Source regions of DMOS transistors}
- H10D 62/155: {Shapes (cell layout of DMOS H10D62/127)}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/60: Impurity distributions or concentrations
- H10D 62/8325: {Silicon carbide}
- H10D 84/0156: {Manufacturing their doped wells}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 30/22: using masks
- H10D 62/153: {Impurity concentrations or distributions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate, a drift layer, a well region, and a source region. The substrate has a first conductivity type. The drift layer has the first conductivity type and is on the substrate. The well region has a second conductivity type opposite the first conductivity type and provides a channel region. The source region is in the well region and has the first conductivity type. A doping concentration of the well region along a surface of the drift layer opposite the substrate is variable such that the well region includes a region of increased doping concentration at a distance from a junction between the source region and the well region.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate, the substrate having a first conductivity type;
a drift layer on the substrate, the drift layer having the first conductivity type;
a well region in the drift layer, wherein:
the well region has a second conductivity type opposite the first conductivity type; and
the well region provides a channel region; and
a source region in the well region, wherein:
the well region is between the source region and the drift layer;
the source region has the first conductivity type; and
the channel region comprises a first region of increased doping concentration at a surface of the drift layer opposite the substrate, and the first region is laterally separated from the source region along the surface of the drift layer by a second region having a laterally constant doping concentration that is lower than the increased doping concentration of the first region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1 wherein a doping concentration of the first region along the surface of the drift layer opposite the substrate increases in proportion to a distance between an interface between the source region and the well region such that the increase in doping concentration is towards an interface between the well region and the drift region along the surface of the drift region opposite the substrate.

### Claim 3 (depends on 1)

The semiconductor device of claim 1 wherein the first region is located along an interface between the well region and the drift region.

### Claim 4 (depends on 3)

The semiconductor device of claim 3 wherein a doping concentration of the first region is between 1.1 and 250 times greater than a doping concentration of the remainder of the well region.

### Claim 5 (depends on 4)

The semiconductor device of claim 4 wherein the doping concentration of the first region is between 2×1017 and 5×1019 cm−3.

### Claim 6 (depends on 5)

The semiconductor device of claim 5 wherein a doping concentration of the second region is between 5×1015 and 5×1017 cm3.

### Claim 7 (depends on 3)

The semiconductor device of claim 3 wherein a distance between the first region and an interface between the source region and the well region is between 0.2 and 2 μm.

### Claim 8 (depends on 3)

The semiconductor device of claim 3 wherein a doping concentration of the first region along the surface of the drift layer opposite the substrate varies in a linear fashion.

### Claim 9 (depends on 3)

The semiconductor device of claim 3 wherein a doping concentration of the first region along the surface of the drift layer opposite the substrate varies in a stepwise fashion.

### Claim 10 (depends on 3)

The semiconductor device of claim 3 wherein a doping concentration of the first region along the surface of the drift layer opposite the substrate varies in an exponential fashion.

### Claim 11 (depends on 1)

The semiconductor device of claim 1 wherein the semiconductor device is a metal-oxide-semiconductor field-effect transistor (MOSFET).

### Claim 12 (depends on 11)

The semiconductor device of claim 11 further comprising:
a drain contact on a surface of the substrate opposite the drift layer;
a source contact on the surface of the drift layer opposite the substrate such that the source contact is in contact with the source region and the well region;
a gate oxide on the surface of the drift layer opposite the substrate such that the gate oxide is in contact with the well region and the source region and separated from the source contact, wherein the channel region of the MOSFET is below the gate oxide in the well region; and
a gate contact on the gate oxide.

### Claim 13 (depends on 1)

The semiconductor device of claim 1 wherein a depth of the source region is non-uniform.

### Claim 14 (depends on 13)

The semiconductor device of claim 13 wherein the depth of the source region increases in proportion to a distance from the channel region.

### Claim 15

A semiconductor device comprising:
a substrate, the substrate having a first conductivity type;
a drift layer on the substrate, the drift layer having the first conductivity type;
a well region in the drift layer, wherein:
the well region has a second conductivity type opposite the first conductivity type; and
the well region provides a channel region; and
a source region in the well region, wherein:
the well region is between the source region and the drift layer;
the source region has the first conductivity type;
the source region comprises a first region of decreased depth compared to a second region of the source region; and
a doping concentration of the source region remains constant across the first region and the second region.

### Claim 16 (depends on 15)

The semiconductor device of claim 15 wherein a depth of the source region increases in proportion to a distance from the channel region.

### Claim 17 (depends on 16)

The semiconductor device of claim 16 wherein the depth of the source region at a first edge of the source region nearest the channel region is between 0.06 and 0.93 times less than the depth of the source region at a second edge of the source region opposite the first edge.

### Claim 18 (depends on 16)

The semiconductor device of claim 16 wherein the depth of the source region varies in a linear fashion.

### Claim 19 (depends on 16)

The semiconductor device of claim 16 wherein the depth of the source region varies in a stepwise fashion.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, wherein the channel region comprises a first region of increased doping concentration at a surface of the drift layer opposite the substrate, and the first region is laterally separated from the source region along the surface of the drift layer by a second region having a laterally constant doping concentration.

### Claim 21

A method for manufacturing a semiconductor device comprising:
providing a substrate having a first conductivity type;
providing a drift layer on the substrate, the drift layer having the first conductivity type;
providing a well region in the drift layer such that:
the well region has a second conductivity type opposite the first conductivity type; and
the well region provides a channel region; and
providing a source region in the well region such that:
the well region is between the source region and the drift layer;
the source region has the first conductivity type; and
the channel region comprises a first region of increased doping concentration at a distance from a junction between the source region and the well region, and the first region is laterally separated from the source region along a lateral surface of the drift layer opposite the substrate by a second region having a laterally constant doping concentration that is lower than the increased doping concentration of the first region.

### Claim 22 (depends on 21)

The method of claim 21 wherein the well region is provided such that a doping concentration of the first region is between 1.1 and 250 times greater than a doping concentration of the second region.

### Claim 23 (depends on 21)

The method of claim 21 wherein a doping concentration of the first region is between 2×1017 and 5×1019 cm−3.

### Claim 24 (depends on 23)

The method of claim 23 wherein a doping concentration of the second region is between 5×1015 and 5×1017 cm−3.

### Claim 25 (depends on 21)

The method of claim 21 wherein the distance between the first region of increased doping concentration and the junction between the source region and the well region is between 0.2 and 2 μm.

### Claim 26 (depends on 21)

The method of claim 21 wherein:
providing the well region comprises providing a well implantation mask on the drift layer and performing an ion implantation process; and
providing the source region comprises providing a source implantation mask on the drift layer and performing an ion implantation process.

### Claim 27 (depends on 26)

The method of claim 26 wherein providing the drift layer comprises growing the drift layer via an epitaxy process.