# US 11,309,411 B2 · Insulated gate bipolar transistor and method of manufacturing same

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- Number: US 11,309,411 B2
- Document ID: US11309411B2
- Status: Granted
- Kind: B2
- Application number: 16/891,433
- Filed: 2020-06-03
- Published: 2021-12-09
- Granted: 2022-04-19
- Earliest claimed: 2020-06-03
- Assignees: DB HiTek Co., Ltd.
- Applicants: DB HiTek Co., Ltd.
- Inventors: Young-Seok Kim
- Web page: https://patentgrep.com/patent/US11309411B2

## CPC

- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 12/01: Manufacture or treatment
- H10D 12/031: {of IGBTs}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/231: {Emitter or collector electrodes for bipolar transistors}
- H10D 64/232: {Emitter electrodes for IGBTs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present invention relates to an insulated gate bipolar transistor (IGBT) and, more particularly, to an insulated gate bipolar transistor that has multiple mesas having different widths, configured to promote the buildup and accumulation of hole carriers, thereby facilitating relatively easy subsequent processing, while maximizing conductivity modulation.

## Claims

### Claim 1

An insulated gate bipolar transistor, comprising:
a collector electrode;
a collector layer on the collector electrode, the collector layer having a first conductivity type;
a buffer layer on the collector layer, the buffer layer having a second conductivity type;
a drift region on the buffer layer, the drift region having the second conductivity type;
a body region on the drift region, the body region having the first conductivity type;
a plurality of trench gates penetrating the body region, configured to separate a first region from a second region in the body region;
an interlayer insulating film covering a surface of the trench gates;
emitters spaced apart from each other on a surface of the body region in the first region, the emitters having the second conductivity type
an emitter electrode on the interlayer insulating film;
a first body contact overlapping each of the emitters in the first region and in contact with the emitter electrode; and
a second body contact on or at the surface of the body region in the second region and in contact with the emitter electrode,
wherein the first region includes a first mesa, the second region is adjacent to the first region and includes a second mesa, and the first mesa has a width larger than that of the second mesa.

### Claim 2 (depends on 1)

The transistor of claim 1, wherein adjacent ones of the trench gates are at boundaries of the first region and the second region.

### Claim 3 (depends on 1)

The transistor of claim 1, wherein each of the first and second body contact regions have the first conductivity type.

### Claim 4 (depends on 1)

The transistor of claim 1, wherein the first region and the second region are repetitive.

### Claim 5 (depends on 1)

The transistor of claim 1, further comprising a plurality of the second regions adjacent to the first region; and
a device isolation layer penetrating the body region, configured to form a boundary between adjacent ones of the second regions in the body region.

### Claim 6 (depends on 1)

The transistor of claim 1, wherein adjacent ones of the trench gates are on boundaries of the first region and the second region, and include a gate insulating layer having an oxide film along an inner wall and a gate electrode on an inner surface of the gate insulating layer.

### Claim 7 (depends on 1)

The transistor of claim 1, wherein a distance between adjacent trench gates at opposite boundaries of the first region is different from a distance between adjacent trench gates at opposite boundaries of the second region.
