# US 11,309,410 B2 · Semiconductor device having active and inactive semiconductor mesas

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- Number: US 11,309,410 B2
- Document ID: US11309410B2
- Status: Granted
- Kind: B2
- Application number: 16/890,822
- Filed: 2020-06-02
- Published: 2020-09-17
- Granted: 2022-04-19
- Earliest claimed: 2013-03-12
- Assignees: Infineon Technologies AG
- Applicants: Infineon Technologies AG
- Inventors: Maria Cotorogea; Frank Wolter; Hans-Joachim Schulze; Franz-Josef Niedernostheide; Yvonne Gawlina-Schmidl
- Web page: https://patentgrep.com/patent/US11309410B2

## CPC

- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10B 99/22: {including field-effect components}
- H10D 12/441: {Vertical IGBTs}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/142: {Anode regions of thyristors or collector regions of gated bipolar-mode devices}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10B 41/30: characterised by the memory core region
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device is described in which a conductive channel is present along an active gate trench of the device when a gate potential is at an on-voltage, whereas no conductive channel is present along an inactive trench of the device for the same gate potential condition.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate;
a first active gate trench extending from a first main surface of the semiconductor substrate and into a transistor body region formed in the semiconductor substrate;
a second active gate trench extending from the first main surface and into the transistor body region; and
a plurality of body trenches extending from the first main surface and into the transistor body region between the first active gate trench and the second active gate trench;
wherein the first active gate trench, the second active gate trench and the body trenches are arranged as parallel stripes in a cell array,
wherein an active semiconductor mesa is delimited by each one of the first and the second active gate trenches and the body trench disposed closest to the corresponding active gate trench, and includes a conductive channel that forms in the transistor body region responsive to an on-voltage provided to the cell array,
wherein an inactive semiconductor mesa is delimited by each adjacent pair of the body trenches, and is devoid of a conductive channel that forms responsive to the on-voltage,
wherein more inactive semiconductor mesas than active semiconductor mesas are provided per unit cell in the cell array.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein at least twice as many inactive semiconductor mesas than active semiconductor mesas are provided per unit cell in the cell array.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein at least one of the inactive semiconductor mesas disposed between the first and the second active gate trenches is delimited by a pair of the body trenches that each include an electrode coupled to a source potential provided to the cell array.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein each body trench in a first subset of the body trenches includes an electrode coupled to a source potential provided to the cell array, wherein each body trench in a second subset of the body trenches includes an electrode coupled to a gate potential that provides the on-voltage, and wherein the first subset and the second subset are mutually exclusive.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein transistor source regions formed in the inactive semiconductor mesas disposed between adjacent ones of the body trenches included in the second subset are disconnected from the source potential.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, wherein at least one of the inactive semiconductor mesas is delimited by a pair of the body trenches included in the first subset.

### Claim 7 (depends on 4)

The semiconductor device of claim 4, wherein a first one of the inactive semiconductor mesas is delimited by a first one and a second one of the body trenches included in the first subset, and wherein a second one of the inactive semiconductor mesas is delimited by the second one of the body trenches included in the first subset and one of the body trenches included in the second subset.

### Claim 8 (depends on 4)

The semiconductor device of claim 4, wherein at least one of the inactive semiconductor mesas is delimited on a first side by a body trench included in the first subset and on a second side opposite the first side by a body trench included in the second subset.

### Claim 9 (depends on 4)

The semiconductor device of claim 4, wherein at least two of the body trenches included in the first subset are interposed between each one of the first and the second active gate trenches and the closest body trench included in the second subset.

### Claim 10 (depends on 4)

The semiconductor device of claim 4, wherein at least twice as many body trenches are included in the first subset than in the second subset.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein transistor source regions formed in the active semiconductor mesas are connected to a source potential provided to the cell array, and wherein transistor source regions formed in the inactive semiconductor mesas disposed between adjacent ones of the body trenches are disconnected from the source potential.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein transistor source regions formed in the active semiconductor mesas are connected to a source potential provided to the cell array, and wherein transistor source regions formed in at least some of the inactive semiconductor mesas are connected to the source potential.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, wherein the body trenches further from the first and the second active gate trenches than other ones of the body trenches are connected to a gate potential that provides the on-voltage, and wherein the body trenches disposed closest to the first and the second active gate trenches are connected to a source potential provided to the cell array.

### Claim 14 (depends on 1)

The semiconductor device of claim 1, wherein the body trenches are identical to each other and to the first and the second active gate trenches.

### Claim 15 (depends on 1)

The semiconductor device of claim 1, wherein the body trenches are identical to each other and different from the first and the second active gate trenches.

### Claim 16 (depends on 1)

The semiconductor device of claim 1, wherein at least one of the body trenches is different from the other body trenches.

### Claim 17 (depends on 1)

The semiconductor device of claim 1, wherein at least one of the body trenches is different from the other body trenches.

### Claim 18 (depends on 1)

The semiconductor device of claim 1, wherein each of the body trenches connected to a gate potential that provides the on-voltage is different from each of the body trenches connected to a source potential provided to the cell array.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein each of the body trenches connected to the gate potential extends deeper into the semiconductor substrate than each of the body trenches connected to the source potential.

### Claim 20 (depends on 1)

The semiconductor device of claim 1, wherein each of the body trenches connected to a gate potential that provides the on-voltage is identical to the first and the second active trenches.

### Claim 21

A semiconductor device, comprising:
a semiconductor substrate;
a unit cell formed in the semiconductor substrate and comprising:
a plurality of active gate trenches extending from a first main surface of the semiconductor substrate and into a transistor body region formed in the semiconductor substrate;
a plurality of body trenches extending from the first main surface and into the transistor body region;
an active semiconductor mesa adjoining each one of the active gate trenches and having a conductive channel that forms in the transistor body region responsive to an on-voltage provided to the unit cell; and
a plurality of inactive semiconductor mesas each delimited by a pair of trenches and being devoid of a conductive channel that forms responsive to the on-voltage provided to the unit cell,
wherein more inactive semiconductor mesas than active semiconductor mesas are provided in the unit cell.