# US 11,309,409 B2 · Pseudo Schottky diode

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- Number: US 11,309,409 B2
- Document ID: US11309409B2
- Status: Granted
- Kind: B2
- Application number: 16/889,893
- Filed: 2020-06-02
- Published: 2021-01-28
- Granted: 2022-04-19
- Earliest claimed: 2019-07-26
- Assignees: Nexperia B.V.
- Applicants: Nexperia B.V.
- Inventors: Tim Böttcher
- Web page: https://patentgrep.com/patent/US11309409B2

## CPC

- H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00)
- H10D 12/211: {Gated diodes}
- H10D 8/045: {of PN junction diodes}
- H10D 12/021: {of gated diodes, e.g. field-controlled diodes [FCD]}
- H10D 62/128: {Anode regions of diodes}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

This disclosure relates to a semiconductor device and corresponding method of manufacturing the semiconductor device. The semiconductor device includes a MOS transistor device die and a SiGe diode. The SiGe diode is integrally arranged on the MOS transistor device die, so that the SiGe diode is electrically connected between a source connection and drain connection of the MOS transistor device die.

## Claims

### Claim 1

A semiconductor device comprising:
a trench gate MOS transistor device die comprising a source connection, a drain connection, an epitaxial layer, a plurality of gate trenches, and a plurality of source contacts adjacent to the plurality of gate trenches;
a body diode, and
a SiGe diode;
wherein the SiGe diode comprises a SiGe layer integrally arranged on and in direct contact with each of the epitaxial layer, the body diode, and the plurality of source contacts of the MOS transistor device die between the plurality of gate trenches, so that the SiGe diode is electrically connected in parallel with the body diode between a source connection and a drain connection of the MOS transistor device die.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the MOS transistor device die further comprises a gate connection, and wherein the gate connection is connected to the plurality of gate trenches and the source connection.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the MOS transistor device die comprises a body diode electrically connected between the source connection and the drain connection.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein the MOS transistor device die comprises a body diode electrically connected between the source connection and the drain connection.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein the body diode comprises a p-type SiGe semiconductor material and an n-type Si semiconductor material.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the SiGe diode comprises a p-type SiGe semiconductor material and an n-type Si semiconductor material.

### Claim 7 (depends on 2)

The semiconductor device of claim 2, wherein the SiGe diode comprises a p-type SiGe semiconductor material and an n-type Si semiconductor material.

### Claim 8 (depends on 3)

The semiconductor device of claim 3, wherein the SiGe diode comprises a p-type SiGe semiconductor material and an n-type Si semiconductor material.

### Claim 9 (depends on 6)

The semiconductor device of claim 6, wherein the p-type SiGe semiconductor material is an epitaxial layer.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the n-type Si semiconductor material is an epitaxial layer.

### Claim 11 (depends on 6)

The semiconductor device of claim 6, further comprising a source metallisation connected to the source connection of the MOS transistor device die and the p-type SiGe semiconductor material of the SiGe diode.

### Claim 12

A method of manufacturing a semiconductor device, the method comprising the steps of: forming a MOS transistor device die comprising a source connection, a drain connection, an epitaxial layer, a plurality of gate trenches, a plurality of source contacts adjacent to the plurality of gate trenches, a body diode, and a SiGe diode; wherein the SiGe diode comprises a SiGe layer integrally formed on and indirect contact with each of the epitaxial layer, the body diode, and the plurality of source contacts of the MOS transistor device die between the plurality of gate trenches, so that the SiGe diode is electrically connected between a source connection and a drain connection of the MOS transistor device die.

### Claim 13 (depends on 12)

The method of claim 12, wherein the MOS transistor device die further comprises a gate connection that is connected to the plurality of gate trenches and the source connection.

### Claim 14 (depends on 12)

The method of claim 12, wherein the MOS transistor device die comprises a body diode electrically connected between the source connection and the drain connection.

### Claim 15 (depends on 13)

The method of claim 13, wherein the MOS transistor device die comprises a body diode electrically connected between the source connection and the drain connection.

### Claim 16 (depends on 12)

The method of claim 12, wherein the SiGe diode is formed of a p-type SiGe semiconductor material and an n-type Si semiconductor material.

### Claim 17 (depends on 13)

The method of claim 13, wherein the SiGe diode is formed of a p-type SiGe semiconductor material and an n-type Si semiconductor material.

### Claim 18 (depends on 16)

The method of claim 16, wherein the p-type SiGe semiconductor material is formed of an epitaxial layer.

### Claim 19 (depends on 18)

The method of claim 18, wherein the n-type Si semiconductor material is formed of an epitaxial layer.

### Claim 20 (depends on 12)

The method of claim 12, further comprising a source metallisation connected to the source connection of the MOS transistor device die and the p-type SiGe semiconductor material of the SiGe diode.