# US 11,309,407 B2 · Methods of manufacturing low-temperature polysilicon thin film and transistor

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- Number: US 11,309,407 B2
- Document ID: US11309407B2
- Status: Granted
- Kind: B2
- Application number: 16/760,068
- Filed: 2017-11-14
- Published: 2021-03-11
- Granted: 2022-04-19
- Earliest claimed: 2017-11-03
- Assignees: Hkc Corporation Limited
- Applicants: Hkc Corporation Limited
- Inventors: Huailiang He
- Web page: https://patentgrep.com/patent/US11309407B2

## CPC

- H10D 30/0316: {of lateral bottom-gate TFTs comprising only a single gate}
- H10P 14/2922: {being non-crystalline insulating materials, e.g. glass or polymers}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6704: {having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6732: {Bottom-gate only TFTs}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10P 14/3238: {being insulating materials}
- H10P 14/3248: {consisting of two layers}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/36: {characterised by treatments done before the formation of the materials}
- H10P 14/3808: {using laser beams}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a low temperature polysilicon thin film includes: forming a buffer layer on a substrate; forming a gate electrode on the buffer layer; forming a patterned raising layer on the gate electrode, wherein the patterned raising layer covers a top surface and a lateral surface of the gate electrode; forming a first diffusion barrier layer on the patterned raising layer; forming a second diffusion barrier layer on the first diffusion barrier layer; forming a silicon layer on the second diffusion barrier layer; annealing the silicon layer to form a polysilicon layer, wherein the polysilicon layer includes a patterned area and a to-be-removed area, the patterned area has the same pattern with the patterned raising layer, and the patterned area is whole directly above the patterned raising layer; and in the polysilicon layer, removing the to-be-removed area, and keeping the patterned area.

## Claims

### Claim 1

A method of manufacturing a low temperature polysilicon thin film, comprising:
forming a buffer layer on a substrate;
forming a gate electrode on the buffer layer;
forming a patterned raising layer on the gate electrode, wherein the patterned raising layer covers a top surface and a lateral surface of the gate electrode;
forming a first diffusion barrier layer on the patterned raising layer;
forming a second diffusion barrier layer on the first diffusion barrier layer;
forming a silicon layer on the second diffusion barrier layer;
annealing the silicon layer to form a polysilicon layer, wherein the polysilicon layer includes a patterned area and a to-be-removed area, the patterned area has the same pattern with the patterned raising layer, and the patterned area is whole directly above the patterned raising layer; and
in the polysilicon layer, removing the to-be-removed area, and keeping the patterned area.

### Claim 2 (depends on 1)

The method according to claim 1, further comprising:
generating defects on an upper surface of the first diffusion barrier layer.

### Claim 3 (depends on 1)

The method according to claim 1, further comprising:
generating defects on an upper surface of the buffer layer.

### Claim 4 (depends on 1)

The method according to claim 1, further comprising:
before forming the second diffusion barrier layer, forming an impurity collection layer on the first diffusion barrier layer and then forming the second diffusion barrier layer on the impurity collection layer.

### Claim 5 (depends on 1)

The method according to claim 1, further comprising:
before annealing, forming an impurity collection layer on the silicon layer.

### Claim 6 (depends on 5)

The method according to claim 5, wherein the impurity collection layer is a low density porous SiOx layer.

### Claim 7 (depends on 5)

The method according to claim 5, wherein pores of the impurity trap functions as a recrystallization growth space.

### Claim 8 (depends on 1)

The method according to claim 1, wherein the buffer layer comprises a plurality of sub-buffer layers.

### Claim 9 (depends on 1)

The method according to claim 1, wherein the annealing is laser annealing.

### Claim 10

A method of manufacturing a low temperature polysilicon thin film, comprising:
forming a buffer layer on a substrate;
forming a gate electrode on the buffer layer;
forming a patterned raising layer on the gate electrode, wherein the patterned raising layer covers a top surface and a lateral surface of the gate electrode;
forming a first diffusion barrier layer on the patterned raising layer;
forming a second diffusion barrier layer on the first diffusion barrier layer;
forming a silicon layer on the second diffusion barrier layer;
forming an impurity collection layer on the silicon layer, wherein the impurity collection layer has pores for impurities diffusing from the substrate;
keeping the impurity collection layer on the silicon layer and annealing by laser beam irradiating the silicon layer to form a polysilicon layer, wherein the polysilicon layer includes a patterned area and a to-be-removed area, the patterned area has the same pattern with the patterned raising layer, and the patterned area is whole directly above the patterned raising layer; and
in the polysilicon layer, removing the to-be-removed area, and keeping the patterned area.

### Claim 11 (depends on 10)

The method according to claim 10, wherein the impurity collection layer is a photoresist or a low density porous SiOx layer, its aperture is smaller than 20 nm, and pores of the impurity trap functions as a recrystallization growth space.

### Claim 12

A method of manufacturing a low temperature polysilicon thin film transistor, comprising the steps of:
forming a buffer layer on a substrate;
forming a gate electrode on the buffer layer;
forming a patterned raising layer on the gate electrode, wherein the patterned raising layer covers a top surface and a lateral surface of the gate electrode;
forming a first diffusion barrier layer on the patterned raising layer;
forming a second diffusion barrier layer on the first diffusion barrier layer;
forming a silicon layer on the second diffusion barrier layer;
annealing the silicon layer to form a polysilicon layer, wherein the polysilicon layer includes a patterned area and a to-be-removed area, the patterned area has the same pattern with the patterned raising layer, and the patterned area is whole directly above the patterned raising layer;
in the polysilicon layer, removing the to-be-removed area, and keeping the patterned area; and
forming a source electrode and a drain electrode, wherein the source electrode and the drain electrode are electrically connected to the polysilicon layer.

### Claim 13 (depends on 12)

The method according to claim 12, further comprising:
generating defects on an upper surface of the first diffusion barrier layer.

### Claim 14 (depends on 12)

The method according to claim 12, further comprising:
generating defects on an upper surface of the buffer layer.

### Claim 15 (depends on 12)

The method according to claim 12, further comprising:
before forming the second diffusion barrier layer, forming an impurity collection layer on the first diffusion barrier layer and then forming the second diffusion barrier layer on the impurity collection layer.

### Claim 16 (depends on 12)

The method according to claim 12, further comprising:
before annealing, forming an impurity collection layer on the silicon layer.

### Claim 17 (depends on 16)

The method according to claim 16, wherein the impurity collection layer is a low density porous SiOx layer.

### Claim 18 (depends on 16)

The method according to claim 16, wherein pores of the impurity trap functions as a recrystallization growth space.

### Claim 19 (depends on 12)

The method according to claim 12, wherein the buffer layer comprises a plurality of sub-buffer layers.

### Claim 20 (depends on 12)

The method according to claim 12, wherein the annealing is laser annealing.