# US 11,309,405 B2 · Vertical field effect transistor device having protruded shallow trench isolation and method for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,405 B2 - Document ID: US11309405B2 - Status: Granted - Kind: B2 - Application number: 16/846,813 - Filed: 2020-04-13 - Published: 2020-12-24 - Granted: 2022-04-19 - Earliest claimed: 2019-06-18 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Hwi Chan Jun; Min Gyu Kim; Seon Bae Kim - Web page: https://patentgrep.com/patent/US11309405B2 ## CPC - H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)} - H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) - H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates} - H10D 84/0151: {Manufacturing their isolation regions} - H10D 84/016: {the components including vertical IGFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/837: {comprising vertical IGFETs} - H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)} - H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)} - H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)} - H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method for manufacturing a vertical field effect transistor (VFET) device may include: providing an intermediate VFET structure including a substrate, a plurality of fin structures formed thereon, and a doped layer formed on the substrate between the fin structures, the doped layer comprising a bottom source/drain (S/D) region; forming a shallow trench through the doped layer and the substrate below a top surface of the substrate and between the fin structures, to isolate the fin structures from each other; filling the shallow trench and a space between the fin structures with an insulating material; etching the insulating material filled between the fin structures above a level of a top surface of the doped layer, except in the shallow trench, such that a shallow trench isolation (STI) structure having a top surface to be at or above a level of the top surface of the doped layer is formed in the shallow trench; forming a plurality of gate structures on the fin structures, respectively; and forming a top S/D region above the fin structures. ## Claims ### Claim 1 A method for manufacturing a vertical field effect transistor (VFET) device, the method comprising: providing an intermediate VFET structure comprising a substrate, a plurality of fin structures formed thereon, and a doped layer formed on the substrate between the fin structures, the doped layer comprising a bottom source/drain (S/D) region, a bottom surface of the fin structures and a bottom surface of the doped layer being on a same plane; forming a shallow trench through the doped layer and the substrate below a top surface of the substrate and between the fin structures, to isolate the fin structures from each other; filling the shallow trench and a space between the fin structures with an insulating material; etching the insulating material filled between the fin structures above a level of a top surface of the doped layer, except in the shallow trench, such that a shallow trench isolation (STI) structure having a top surface at or above the level of the top surface of the doped layer is formed in the shallow trench; forming a plurality of gate structures on the fin structures, respectively; and forming a top S/D region above the fin structures, wherein the intermediate VFET structure further comprises a bottom spacer formed on the doped layer between the fin structures, wherein the shallow trench is formed through the bottom spacer, the doped layer and the substrate between the fin structures, and wherein the STI structure is formed in the shallow trench such that the top surface of the STI structure is positioned at or above a level of a top surface of the bottom spacer. ### Claim 2 (depends on 1) The method of claim 1, wherein the STI structure has a protrusion protruded above the level of the top surface of the doped layer. ### Claim 3 (depends on 1) The method of claim 1, further comprising inserting a recess delay structure in the insulating material at a position above the shallow trench prior to the etching the insulating material. ### Claim 4 (depends on 3) The method of claim 3, wherein the recess delay structure is inserted in the insulating material at a level same as a level of top surfaces of the fin structures. ### Claim 5 (depends on 3) The method of claim 3, wherein the insulating material and a material forming the recess delay structure have etch selectivity against each other. ### Claim 6 (depends on 5) The method of claim 5, wherein the insulating material is formed of a dielectric oxide material. ### Claim 7 (depends on 5) The method of claim 5, wherein the recess delay structure is formed of a material comprising a silicon nitride. ### Claim 8 A method for manufacturing a vertical field effect transistor (VFET) device, the method comprising: providing an intermediate VFET structure comprising a substrate, a plurality of fin structures formed thereon, and a doped layer formed on the substrate between the fin structures, the doped layer comprising a bottom source/drain (S/D) region, a bottom surface of the fin structures and a bottom surface of the doped layer being on a same plane; forming a shallow trench through the doped layer and the substrate below a top surface of the substrate and between the fin structures, to isolate the fin structures from each other; filling the shallow trench and a space between the fin structures with an insulating material; etching the insulating material filled between the fin structures above a level of a top surface of the doped layer, except in the shallow trench, such that a shallow trench isolation (STI) structure having a top surface at or above the level of the top surface of the doped layer is formed in the shallow trench; forming a plurality of gate structures on the fin structures, respectively; and forming a top S/D region above the fin structures, wherein the etching the insulating material is performed such that the insulating material at a position above the shallow trench is delay-etched compared to the insulating material at positions between the shallow trench and the fin structures. ### Claim 9 A method for manufacturing a vertical field effect transistor (VFET) device, the method comprising: providing an intermediate VFET structure comprising a substrate, a plurality of fin structures formed thereon, and a doped layer formed on the substrate between the fin structures, the doped layer comprising a bottom source/drain (S/D) region, a bottom surface of the fin structures and a bottom surface of the doped layer being on a same plane; forming a shallow trench through the doped layer and the substrate below a top surface of the substrate and between the fin structures, to isolate the fin structures from each other; filling the shallow trench and a space between the fin structures with an insulating material; etching the insulating material filled between the fin structures above a level of a top surface of the doped layer, except in the shallow trench, such that a shallow trench isolation (STI) structure having a top surface at or above the level of the top surface of the doped layer is formed in the shallow trench; forming a plurality of gate structures on the fin structures, respectively; and forming a top S/D region above the fin structures, wherein the method further comprises forming a bottom spacer on the doped layer between the fin structure and on the top surface of the STI structure after the etching the insulating material. ### Claim 10 (depends on 9) The method of claim 9, wherein a top surface of the bottom spacer on the top surface of the STI structure is higher than a top surface of the bottom spacer on the doped layer. ### Claim 11 A method for manufacturing a vertical field effect transistor (VFET) device, the method comprising: providing an intermediate VFET structure comprising a substrate, a plurality of fin structures formed thereon, and a doped layer formed on the substrate between the fin structures, the doped layer comprising a bottom source/drain (S/D) region; forming a shallow trench through the doped layer and the substrate below a top surface of the substrate and between the fin structures, to isolate the fin structures from each other; filling a space between the fin structures including the shallow trench with an insulating material; etching the insulating material such that the insulating material filled between the fin structure and above the shallow trench is delay-etched compared to the insulating material filled in positions between the shallow trench and the fin structures to form a shallow trench isolation (STI) structure in the shallow trench; forming a plurality of gate structures on the fin structures, respectively; and forming a top S/D region above the fin structure. ### Claim 12 (depends on 11) The method of claim 11, wherein the STI structure has a protrusion protruded above a level of a top surface of the doped layer. ### Claim 13 A vertical field effect transistor (VFET) device comprising: a substrate; a doped layer formed on the substrate by doping impurities, the doped layer comprising a bottom source/drain (S/D) region; a bottom spacer formed on the doped layer; a plurality of fin structures vertically formed on the substrate above the doped layer; a plurality gate structures respectively surrounding the fin structures; a top S/D region formed above the fin structures; a shallow trench isolation (STI) structure filling a shallow trench formed through the doped layer and the substrate below a top surface of the substrate and between the fin structures and an interlayer dielectric (ILD) structure separately formed above the STI structure and between the gate structures, wherein a top surface of the STI structure is at or above a level of a top surface of the bottom spacer, wherein a bottom surface of the fin structures and a bottom surface of the doped layer are on a same plane. ### Claim 14 (depends on 13) The VFET device of claim 13, wherein the STI structure has a protrusion protruded above the level of the top surface of the doped layer. ### Claim 15 (depends on 14) The VFET device of claim 14, wherein the protrusion of the STI structure takes a shape of trapezoid above the level of the top surface of the doped layer. ### Claim 16 (depends on 13) The VFET device of claim 13, wherein the STI structure is a structure formed before the gate structures are formed to surround the fin structures. ### Claim 17 (depends on 16) The VFET device of claim 16, wherein the STI structure has a protrusion protruded above the level of the top surface of the bottom spacer. ### Claim 18 A vertical field effect transistor (VFET) device comprising: a substrate; a doped layer formed on the substrate by doping impurities, the doped layer comprising a bottom source/drain (S/D) region; a plurality of fin structures vertically formed on the substrate above the doped layer; a top S/D region formed above the fin structures; and a shallow trench isolation (STI) structure filling a shallow trench formed through the doped layer and the substrate below a top surface of the substrate and between the fin structures, wherein a top surface of the STI structure is at or above a level of a top surface of the doped layer, wherein a bottom surface of the fin structures and a bottom surface of the doped layer are on a same plane, and wherein the VFET further comprises a bottom spacer formed on the doped layer and the top surface of the STI structure.