# US 11,309,404 B2 · Integrated CMOS source drain formation with advanced control

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- Number: US 11,309,404 B2
- Document ID: US11309404B2
- Status: Granted
- Kind: B2
- Application number: 16/502,555
- Filed: 2019-07-03
- Published: 2020-01-09
- Granted: 2022-04-19
- Earliest claimed: 2018-07-05
- Assignees: Applied Materials, Inc.
- Applicants: Applied Materials, Inc.
- Inventors: Benjamin Colombeau; Tushar Mandrekar; Patricia M. Liu; Suketu Arun Parikh; Matthias Bauer; Dimitri R. Kioussis; Sanjay Natarajan; Abhishek Dube
- Web page: https://patentgrep.com/patent/US11309404B2

## CPC

- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/27: {using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials}
- H10P 14/271: {characterised by the preparation of substrate for selective deposition}
- H10P 14/3404: {being Group IVA materials}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3442: {N-type}
- H10P 14/3444: {P-type}
- H10P 14/3462: {Nanowires}
- H10P 50/242: {of Group IV materials}
- H10P 72/0454: {surrounding a central transfer chamber}
- H10P 72/0464: {characterised by the construction of the transfer chamber}
- H10P 72/0604: {Process monitoring, e.g. flow or thickness monitoring}
- H10P 72/3302: {Mechanical parts of transfer devices}
- H10P 72/7602: {the wafers being placed on a robot blade or gripped by a gripper for conveyance}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

## Claims

### Claim 1

A method of forming a semiconductor device, the method comprising:
performing an anisotropic etch process on a semiconductor material on a semiconductor substrate to expose a surface in the semiconductor material, the surface disposed between an existing structure of the semiconductor device and a bulk semiconductor portion of the semiconductor substrate on which the semiconductor material is formed;
performing an isotropic etch process on an exposed sidewall to recess the semiconductor material that is disposed between the existing structure and the bulk semiconductor portion of the semiconductor substrate by a distance to form a cavity;
in situ measuring the distance that the semiconductor material has been recessed after isotropic etch;
forming a layer of deposited material via a selective epitaxial growth (SEG) process on a surface of the cavity, the substrate not subjected to a pre-clean process between formation of the cavity and SEG;
adjusting the SEG process based on the distance that the semiconductor material has been recessed; and
forming a doped region on the layer of deposited material via a selective epitaxial growth (SEG) process, wherein the doped region comprises one or more of phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), lithium (Li), boron (B), aluminum (Al), gallium (Ga), and indium (In), the doped region having a dopant concentration in a range of about 1×1020 atoms/cm3 to about 1×1022 atoms/cm3,
wherein the isotropic etch process, the SEG process, and the in situ measuring are performed in a single platform under vacuum processing.

### Claim 2 (depends on 1)

The method of claim 1, wherein the isotropic etch occurs in a first process chamber and the method further comprises moving the substrate from the first process chamber to a second process chamber for the SEG process.

### Claim 3 (depends on 1)

The method of claim 1, further comprising epitaxial growing a portion of the semiconductor material prior to forming the layer of deposited material.

### Claim 4 (depends on 1)

The method of claim 1, wherein the distance that the semiconductor material has been recessed is measured by refractometry.

### Claim 5 (depends on 1)

The method of claim 1, wherein the isotropic etch process comprises an etch process selective to the semiconductor material.

### Claim 6 (depends on 5)

The method of claim 5, wherein the isotropic etch process comprises a chemical vapor etch process that includes exposing the exposed sidewall to at least one of HCl, GeH4 or and Cl2.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the layer of deposited material comprises filling the cavity with the deposited material.

### Claim 8 (depends on 1)

The method of claim 1, further comprising, prior to forming the layer of deposited material, depositing a carbon-containing material on the surface of the cavity, wherein the carbon-containing material includes a silicon-carbon-phosphorus (SiCP) material.

### Claim 9 (depends on 8)

The method of claim 8, wherein the SiCP material includes in the range of about 0.1 to 2.0 atomic percent carbon and in the range of about about 1×1020 atoms/cm3 to 1×1021 atoms/cm3 phosphorus.

### Claim 10 (depends on 1)

The method of claim 1, wherein performing the isotropic etch process on the exposed sidewall to form the cavity in the semiconductor material comprises removing semiconductor material until a portion of the semiconductor material that comprises a phosphorus-doped bulk semiconductor material is exposed.

### Claim 11 (depends on 1)

The method of claim 1, wherein the deposited material comprises an n-type dopant comprising arsenic (As), and the selective epitaxial growth (SEG) process includes exposing the surface of the cavity to at least one of AsCl3, TBA, or AsH3 and at least one of dichlorosilane (DCS), HCl, SiH4, Si2H6, or Si4H10.

### Claim 12 (depends on 11)

The method of claim 11, wherein forming the layer of deposited material comprises filling the cavity with arsenic-doped material having an arsenic concentration sufficient to produce a targeted tensile strain within the deposited material.

### Claim 13 (depends on 1)

The method of claim 1, wherein the deposited material comprises a p-type dopant comprising boron (B), and the selective epitaxial growth (SEG) process includes exposing the surface of the cavity to one or more of borane, diborane or plasmas thereof.

### Claim 14 (depends on 1)

The method of claim 1, wherein the layer of additional deposited material is formed without exposing the layer of deposited material formed on the surface of the cavity to air.