# US 11,309,400 B2 · Stacked thin film transistors with nanowires

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- Number: US 11,309,400 B2
- Document ID: US11309400B2
- Status: Granted
- Kind: B2
- Application number: 16/650,153
- Filed: 2018-01-12
- Published: 2020-07-16
- Granted: 2022-04-19
- Earliest claimed: 2018-01-12
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Seung Hoon Sung; Abhishek A. Sharma; Van H. Le; Gilbert Dewey; Jack T. Kavalieros; Tahir Ghani
- Web page: https://patentgrep.com/patent/US11309400B2

## CPC

- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/119: {Nanowire, nanosheet or nanotube semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/875: {being semiconductor metal oxide, e.g. InGaZnO (Group II-VI materials H10D62/86; Group I-VI materials H10D62/871; Pb compounds or alloys H10D62/874)}
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Thin film transistor structures and processes are disclosed that include stacked nanowire bodies to mitigate undesirable short channel effects, which can occur as gate lengths scale down to sub-100 nanometer (nm) dimensions, and to reduce external contact resistance. In an example embodiment, the disclosed structures employ a gate-all-around architecture, in which the gate stack (including a high-k dielectric layer) wraps around each of the stacked channel region nanowires (or nanoribbons) to provide improved electrostatic control. The resulting increased gate surface contact area also provides improved conduction. Additionally, these thin film structures can be stacked with relatively small spacing (e.g., 1 to 20 nm) between nanowire bodies to increase integrated circuit transistor density. In some embodiments, the nanowire body may have a thickness in the range of 1 to 20 nm and a length in the range of 5 to 100 nm.

## Claims

### Claim 1

An integrated circuit (IC) comprising:
a body including an oxide semiconductor material including first, second, and third portions, the second portion between the first and third portions, the first portion being a source region and the third portion being a drain region, and the second portion having a cross-section with a maximum lateral width greater than a maximum vertical height;
a gate dielectric structure wrapped around the second portion of the body; and
a gate electrode structure wrapped around the gate dielectric structure, the gate electrode structure comprising metal.

### Claim 2 (depends on 1)

The IC of claim 1, further comprising one or more additional bodies, the gate dielectric structure wrapped around the additional bodies.

### Claim 3 (depends on 2)

The IC of claim 2, wherein the body and the one or more additional bodies are spaced apart from each other by a distance in the range of 1 nanometer to 20 nanometers.

### Claim 4 (depends on 2)

The IC of claim 2, wherein the number of additional bodies is in the range of 1 to 10.

### Claim 5 (depends on 1)

The IC of claim 1, wherein the gate dielectric structure comprises a high-k dielectric material including hafnium.

### Claim 6 (depends on 1)

The IC of claim 1, wherein the oxide semiconductor material includes indium, gallium, zinc, and oxygen.

### Claim 7 (depends on 1)

The IC of claim 1, wherein the oxide semiconductor material includes at least one of zinc oxide, indium oxide, aluminum zinc oxide, gallium oxide, indium zinc oxide, indium tin oxide, copper oxide, and zinc tin oxide.

### Claim 8 (depends on 1)

The IC of claim 1, wherein the gate electrode structure includes titanium and nitrogen.

### Claim 9 (depends on 1)

The IC of claim 1, wherein the second portion of the body is thinner than at least one of the source region and the drain region.

### Claim 10 (depends on 1)

The IC of claim 1, wherein at least one of the first and third portions of the body includes a higher concentration of oxygen vacancies in the oxide semiconductor material, relative to the second portion.

### Claim 11 (depends on 1)

The IC of claim 1, further comprising a first contact structure wrapped around the first portion of the body, and a second contact structure wrapped around the third portion of the body, the first and second contact structures comprising metal.

### Claim 12 (depends on 11)

The IC of claim 11, further comprising at least one of a first gate spacer between the gate electrode structure and the first contact structure and a second gate spacer between the gate electrode structure and the second contact structure.

### Claim 13 (depends on 1)

The IC of claim 1, wherein:
a thickness of the body in a vertical direction is in a range of 1 nanometer to 20 nanometers; and
a length of the body in a horizontal direction from the source region to the drain region is in the range of 5 nanometers to 100 nanometers, as measured from respective outermost portions of the source and drain regions.

### Claim 14 (depends on 1)

A computing system comprising the IC of claim 1.

### Claim 15

An integrated circuit (IC) comprising:
a first body of oxide semiconductor material, the first body including first, second, and third portions, the second portion of the first body between the first and third portions of the first body, the first portion of the first body being a first source region and the third portion of the first body being a first drain region, and the second portion of the first body having a cross-section with a maximum lateral width greater than a maximum vertical height;
a second body of oxide semiconductor material, the second body including first, second, and third portions, the second portion of the second body between the first and third portions of the second body, the first portion of the second body being a second source region and the third portion of the second body being a second drain region, the second portion of the second body having a cross-section with a maximum lateral width greater than a maximum vertical height, and the second body being below the first body; and
a gate structure that wraps around the second portions of the first and second bodies.

### Claim 16 (depends on 15)

The IC of claim 15, wherein the gate structure comprises:
a gate dielectric that includes a high-k dielectric material including hafnium; and
a gate electrode that includes titanium and nitrogen.

### Claim 17 (depends on 15)

The IC of claim 15, wherein the oxide semiconductor material includes oxygen and one or more of indium, gallium, zinc, aluminum, tin, copper, arsenic, phosphorus, silicon, and germanium.

### Claim 18 (depends on 15)

The IC of claim 15, wherein the gate structure comprises:
a gate dielectric that includes a high-k dielectric material; and
a gate electrode.

### Claim 19 (depends on 15)

The IC of claim 15, wherein at least one of the first and third portions of the first body or the second body includes a higher concentration of oxygen vacancies in the oxide semiconductor material, relative to the second portion.

### Claim 20

An integrated circuit (IC) comprising:
a first body of oxide semiconductor material, the first body including first, second, and third portions, the second portion of the first body between the first and third portions of the first body, the first portion of the first body being a first source region and the third portion of the first body being a first drain region, and the second portion having a cross-section with a maximum lateral width greater than a maximum vertical height;
a second body of oxide semiconductor material, the second body including first, second, and third portions, the second portion of the second body between the first and third portions of the second body, the first portion of the second body being a second source region and the third portion of the second body being a second drain region, the second body being below the first body;
a gate structure that wraps around the second portions of the first and second bodies;
a first contact structure that wraps around the first portions of the first and second bodies; and
a second contact structure that wraps around the third portions of the first and second bodies, the first and second contact structures comprising metal.