# US 11,309,398 B2 · Semiconductor device and manufacturing method for the semiconductor device

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- Number: US 11,309,398 B2
- Document ID: US11309398B2
- Status: Granted
- Kind: B2
- Application number: 16/837,932
- Filed: 2020-04-01
- Published: 2021-10-07
- Granted: 2022-04-19
- Earliest claimed: 2020-04-01
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Chun-Yen Peng; Te-Yang Lai; Bo-Feng Young; Chih-Yu Chang; Sai-Hooi Yeong; Chi On Chui
- Web page: https://patentgrep.com/patent/US11309398B2

## CPC

- H10D 64/689: {having ferroelectric layers}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 64/0134: {with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10P 14/6544: {to change the morphology of the insulating materials, e.g. transformation of an amorphous layer into a crystalline layer}
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a semiconductor device, including a substrate, a fin over the substrate, a multilayer gate dielectric stack over the fin, wherein the multilayer gate dielectric stack includes a first ferroelectric layer, and a first dielectric layer coupled to the first ferroelectric layer, and a gate over the multilayer gate dielectric stack.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a fin over the substrate;
a multilayer gate dielectric stack over the fin, wherein the multilayer gate dielectric stack comprises:
a first ferroelectric layer; and
a first dielectric layer coupled to the first ferroelectric layer, wherein a portion of the first dielectric layer is in direct contact with the first ferroelectric layer, the first ferroelectric layer comprises:
a first portion made of a ferroelectric material in orthorhombic phase;
a second portion made of the ferroelectric material in monoclinic phase; and
a third portion made of the ferroelectric material in tetragonal phase, wherein a total volume of the second portion is greater than a total volume of the first portion, and the total volume of the first portion is greater than a total volume of the third portion; and
a gate over the multilayer gate dielectric stack.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first dielectric layer is spacing between the first ferroelectric layer and the substrate.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first ferroelectric layer is spacing between the first dielectric layer and the substrate.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the multilayer gate dielectric stack further comprises a second ferroelectric layer between the first ferroelectric layer and the gate.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the first ferroelectric layer covers a sidewall of the fin.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising a spacer at least partially surrounding the multilayer gate dielectric stack.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the first ferroelectric layer material comprises crystalized grain.

### Claim 8 (depends on 6)

The semiconductor device of claim 6, further comprising a capping layer over the gate and at least partially surrounded by the spacer laterally.

### Claim 9

A method for forming a semiconductor structure, comprising:
forming a fin over a substrate;
forming a multilayer gate dielectric stack over the fin, wherein the multilayer gate dielectric stack comprises a first ferroelectric layer and a first dielectric layer coupled to the first ferroelectric layer, wherein forming the multilayer gate dielectric stack comprises:
forming a ferroelectric material;
performing an annealing operation to convert the ferroelectric material from an amorphous state to the first ferroelectric layer having a crystalized state, wherein the ferroelectric layer comprises a first portion with orthorhombic phase, a second portion with monoclinic phase, and a third portion with tetragonal phase, wherein a total volume of the first portion is less than a total volume of the second portion, and the total volume of the first portion is greater than a total volume of the third portion; and
forming a gate over the multilayer gate dielectric stack.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
forming a dummy gate over the fin;
forming a spacer at least partially surrounding the dummy gate laterally; and
removing the dummy gate prior to forming the multilayer gate dielectric stack.

### Claim 11 (depends on 9)

The method of claim 9, wherein forming the multilayer gate dielectric stack further comprising:
annealing the first dielectric layer and the first ferroelectric layer simultaneously.

### Claim 12 (depends on 9)

The method of claim 9, further comprising performing a planarization operation over the gate to expose a top surface of the multilayer gate dielectric stack.

### Claim 13 (depends on 9)

The method of claim 9, wherein forming the multilayer gate dielectric stack further comprising forming the first dielectric layer over the first ferroelectric layer and a second ferroelectric layer over the first dielectric layer.

### Claim 14

A method for forming a semiconductor structure, comprising:
forming a fin over a substrate;
forming a plurality of mandrels over the fin;
forming a multilayer gate dielectric stack over a surface of the fin exposed from the mandrels, wherein the multilayer gate dielectric stack comprises a first ferroelectric layer and a first dielectric layer coupled to the first ferroelectric layer, wherein the first ferroelectric layer comprises a first portion with orthorhombic phase, a second portion with monoclinic phase, and a third portion with tetragonal phase, wherein a total volume of the first portion is less than a total volume of the second portion, and the total volume of the first portion is greater than a total volume of the third portion;
forming a gate between two portions of the multilayer gate dielectric stack;
partially removing an upper portion of the gate, thereby an uppermost surface of the gate is lower than an uppermost surface of the mandrels; and
removing the mandrels.

### Claim 15 (depends on 14)

The method of claim 14, wherein forming the multilayer gate dielectric stack further comprising forming a second ferroelectric layer over the first dielectric layer.

### Claim 16 (depends on 14)

The method of claim 14, further comprising
partially removing an upper portion of the multilayer gate dielectric stack; and
forming a hard mask layer over the gate and the multilayer gate dielectric stack.

### Claim 17 (depends on 14)

The method of claim 14, further comprising annealing the multilayer gate dielectric stack to convert a portion of the first ferroelectric layer to a crystalized phase.

### Claim 18 (depends on 14)

The method of claim 14, wherein a portion of the multilayer gate dielectric stack is removed during the removal of the mandrels.

### Claim 19 (depends on 14)

The method of claim 14, wherein the multilayer gate dielectric stack is formed to cover each sidewall of the plurality of mandrels.

### Claim 20 (depends on 14)

The method of claim 14, wherein the first ferroelectric layer comprises a first portion with orthorhombic phase, a second portion with monoclinic phase, and a third portion with tetragonal phase, wherein a total volume of the first portion is less than a total volume of the second portion, and the total volume of the first portion is greater than a total volume of the third portion.