# US 11,309,397 B2 · Contact over active gate employing a stacked spacer

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- Number: US 11,309,397 B2
- Document ID: US11309397B2
- Status: Granted
- Kind: B2
- Application number: 16/672,789
- Filed: 2019-11-04
- Published: 2020-02-27
- Granted: 2022-04-19
- Earliest claimed: 2018-04-10
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng
- Web page: https://patentgrep.com/patent/US11309397B2

## CPC

- H10D 64/687: {having cavities, e.g. porous gate dielectrics having gasses therein}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/679: {comprising air gaps}
- H10W 10/021: {of air gaps}
- H10W 10/20: Air gaps
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/0698: {Local interconnections}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/46: comprising air gaps
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method is presented for employing contact over active gate to reduce parasitic capacitance. The method includes forming high-k metal gates (HKMGs) between stacked spacers, the stacked spacers including a low-k dielectric lower portion and a sacrificial upper portion, forming a first dielectric over the HKMGs, forming first contacts to source/drain of a transistor between the HKMGs, and forming a second dielectric over the first contacts. The method further includes selectively removing the first dielectric to form second contacts to the HKMGs, selectively removing the second dielectric to form third contacts on top of the first contacts, removing the sacrificial upper portion of the stacked spacers, and depositing a third dielectric that pinches off the remaining first and second dielectrics to form air-gaps between the first contacts and the HKMGs.

## Claims

### Claim 1

A method for employing contact over active gate to reduce parasitic capacitance, the method comprising:
forming high-k metal gates (HKMGs) between stacked spacers;
forming a first dielectric over the HKMGs;
forming first contacts to a source/drain of a transistor between the HKMGs;
forming a second dielectric over the first contacts;
selectively removing the first dielectric to form second contacts to the HKMGs;
selectively removing the second dielectric to form third contacts on top of the first contacts; and
depositing a third dielectric that pinches off the remaining first and second dielectrics to form air-gaps on opposed ends of the first contact, an entirety of the air-gaps vertically aligned directly over a common source/drain region and extending above a top surface of the first contact.

### Claim 2 (depends on 1)

The method of claim 1, wherein the stacked spacers include a low-k dielectric lower portion and a sacrificial upper portion.

### Claim 3 (depends on 2)

The method of claim 2, further comprising removing the sacrificial upper portion of the stacked spacers after selectively removing the second dielectric.

### Claim 4 (depends on 3)

The method of claim 3, wherein the low-k dielectric lower portion defines a first length and the sacrificial upper portion defines a second length, where the second length is greater than the first length.

### Claim 5 (depends on 4)

The method of claim 4, wherein the first dielectric has a first thickness and the second dielectric has a second thickness, the first and second thickness being different from each other.

### Claim 6 (depends on 5)

The method of claim 5, further comprising forming the sacrificial upper portion from amorphous silicon (a-Si).

### Claim 7 (depends on 1)

The method of claim 1, wherein the air-gaps extend parallel to a portion of the HKMGs and a portion of the first and second dielectrics.

### Claim 8 (depends on 1)

The method of claim 1, wherein the sacrificial upper portion enables physical isolation between the second and third contacts.

### Claim 9 (depends on 1)

The method of claim 1, wherein the third dielectric wraps around the first and second dielectrics.

### Claim 10

A method for reducing parasitic capacitance, the method comprising:
forming high-k metal gates (HKMGs) between spacers having an upper portion and a lower portion;
forming metal gate caps over the HKMGs;
forming first contacts to a source/drain of a transistor between the HKMGs, the lower portion of the spacers, on opposed ends of a first contact of the first contacts, directly contacting a topmost surface of a common source/drain;
forming dielectric caps over the first contacts;
selectively removing the metal gate caps to form second contacts to the HKMGs;
selectively removing the dielectric caps to form third contacts directly contacting an entirety of an upper surface of the first contacts; and
forming air-gaps on opposed ends of the first contact, an entirety of the air-gaps vertically aligned directly over the common source/drain and extending above a top surface of the first contact.

### Claim 11 (depends on 10)

The method of claim 10, wherein the air-gaps are formed within a dielectric.

### Claim 12 (depends on 11)

The method of claim 11, wherein the dielectric completely surrounds the third contacts.

### Claim 13 (depends on 10)

The method of claim 10, wherein the lower portion of the spacers is a low-k dielectric.

### Claim 14 (depends on 10)

The method of claim 10, wherein the upper portion of the spacers is a sacrificial amorphous silicon (a-Si).

### Claim 15 (depends on 10)

The method of claim 10, wherein the air-gaps are oval-shaped.

### Claim 16 (depends on 10)

The method of claim 10, wherein the metal gate caps have a first thickness and the dielectric caps have a second thickness, the first and second thickness being different from each other.

### Claim 17 (depends on 10)

The method of claim 10, wherein the air-gaps extend parallel to a portion of the HKMGs.

### Claim 18 (depends on 10)

The method of claim 10, wherein the air-gaps extend parallel to a portion of the metal gate caps and the dielectric caps.

### Claim 19 (depends on 10)

The method of claim 10, wherein the upper portion of the spacers enables physical isolation between the second and third contacts.

### Claim 20 (depends on 10)

The method of claim 10, wherein the third contact occupies are greater space than the first contact.