# US 11,309,396 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 11,309,396 B2
- Document ID: US11309396B2
- Status: Granted
- Kind: B2
- Application number: 16/683,486
- Filed: 2019-11-14
- Published: 2020-03-12
- Granted: 2022-04-19
- Earliest claimed: 2017-09-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Wei-Hao Wu; Zhi-Chang Lin; Ting-Hung Hsu; Kuan-Lun Cheng
- Web page: https://patentgrep.com/patent/US11309396B2

## CPC

- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 86/215: {comprising FinFETs}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a first device formed over a substrate. The first device includes a first gate stack encircling a first nanostructure, and the first device is a logic circuit device. The semiconductor device includes a second device formed over the first device. The second device includes a second gate stack encircling a second nanostructure, and the second device is a static random access memory (SRAM).

## Claims

### Claim 1

A semiconductor device, comprising:
a first device formed over a substrate, wherein the first device comprises a first gate stack encircling a first nanostructure, and the first device is a logic circuit device; and
a second device formed over the first device, wherein the second device comprises a second gate stack encircling a second nanostructure, and the second device is a static random access memory (SRAM),
wherein the first gate stack comprises a first portion and a second portion, the first portion is next to a sidewall of the second gate stack, and the second portion is directly below the second gate stack.

### Claim 2 (depends on 1)

The semiconductor device as claimed in claim 1, wherein one of the first and the second device is a p-type device and the other of the first and the second device is an n-type device.

### Claim 3 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising:
an etch stop layer between the first nanostructure and the second nanostructure.

### Claim 4 (depends on 3)

The semiconductor device as claimed in claim 3, further comprising:
a first epitaxy structure wrapping an end of the first nanostructure; and
a second epitaxy structure wrapping an end of the second nanostructure, wherein the etch stop layer is between the first epitaxy structure and the second epitaxy structure.

### Claim 5 (depends on 4)

The semiconductor device as claimed in claim 4, further comprising:
a first contact wrapping the first epitaxy structure;
a second contact wrapping the second epitaxy structure; and
a contact spacer between the first contact and the second contact.

### Claim 6 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising:
an inner gate spacer between the first gate stack and the second gate stack.

### Claim 7 (depends on 1)

The semiconductor device as claimed in claim 1, wherein a topmost surface of the first gate stack is substantially coplanar with a topmost surface of the second gate stack.

### Claim 8 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising:
an isolation structure formed over the substrate; and
an inner gate spacer extending above the substrate, wherein a top surface of the inner gate spacer is higher than a top surface of the isolation structure.

### Claim 9 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising:
an inner gate spacer extending above the substrate, wherein the inner gate spacer is in direct contact with the first gate stack.

### Claim 10

A semiconductor device, comprising:
a first device formed over a substrate, wherein the first device comprises a plurality of first nanostructures stacked in a vertical direction;
a second device formed over the first device, wherein the second device comprises a plurality of second nanostructures stacked in the vertical direction, and one of the first and the second device is a p-type device and the other of the first and the second device is an n-type device;
an isolation structure formed over the substrate; and
a first inner gate spacer extending above the substrate, wherein a top surface of the first inner gate spacer is higher than a top surface of the isolation structure.

### Claim 11 (depends on 10)

The semiconductor device as claimed in claim 10, further comprising:
a first gate stack structure wrapping the first nanostructures, wherein the first gate stack structure has a L-shaped structure; and
a second gate stack structure wrapping the second nanostructures.

### Claim 12 (depends on 11)

The semiconductor device as claimed in claim 11, further comprising:
a second inner gate spacer between the first gate stack structure and the second gate stack structure.

### Claim 13 (depends on 10)

The semiconductor device as claimed in claim 10, further comprising:
a first epitaxy structure formed on opposite sides of the first nanostructures;
a second epitaxy structure formed on opposite sides of the second nanostructures; and
an etch stop layer between the first epitaxy structure and the second epitaxy structure.

### Claim 14 (depends on 13)

The semiconductor device as claimed in claim 13, further comprising:
a first contact wrapping the first epitaxy structure;
a second contact wrapping the second epitaxy structure; and
a contact spacer between the first contact and the second contact.

### Claim 15 (depends on 14)

The semiconductor device as claimed in claim 14, further comprising:
a dielectric layer formed over the etch stop layer, wherein the dielectric layer is between the etch stop layer and the second contact.

### Claim 16 (depends on 10)

The semiconductor device as claimed in claim 10, further comprising:
a first gate stack structure wrapping the first nanostructures, wherein the first inner gate spacer is in direct contact with the first gate stack structure.

### Claim 17

A semiconductor device, comprising:
a first device formed over a substrate, wherein the first device comprises a plurality of first nanostructures stacked and spaced from each other;
a second device formed over the first device, wherein the second device comprises a plurality of second nanostructures stacked and spaced from each other; and
an inner gate spacer between the first nanostructures and the second nanostructures.

### Claim 18 (depends on 17)

The semiconductor device as claimed in claim 17, wherein the first device is a logic circuit device and the second device is a static random access memory (SRAM).

### Claim 19 (depends on 17)

The semiconductor device as claimed in claim 17, further comprising:
a first gate stack structure wrapping the first nanostructures, wherein the first gate stack structure has a L-shaped structure; and
a second gate stack structure wrapping the second nanostructures.

### Claim 20 (depends on 17)

The semiconductor device as claimed in claim 17, wherein the first device further comprises a first epitaxy structure, the second device further comprises a second epitaxy structure, and an etching stop layer is between the first epitaxy structure and the second epitaxy structure.