# US 11,309,395 B2 · 1.5T SONOS memory structure and manufacturing method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,395 B2 - Document ID: US11309395B2 - Status: Granted - Kind: B2 - Application number: 16/826,554 - Filed: 2020-03-23 - Published: 2021-05-13 - Granted: 2022-04-19 - Earliest claimed: 2019-11-12 - Assignees: Shanghai Huali Microelectronics Corporation - Applicants: Shanghai Huali Microelectronics Corporation - Inventors: Xiaoliang Tang - Web page: https://patentgrep.com/patent/US11309395B2 ## CPC - H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate} - H10B 43/30: characterised by the memory core region - H10D 30/0212: {using self-aligned silicidation} - H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors} - H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors - H10D 64/037: {comprising charge-trapping insulators} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES ## Abstract The present invention provides a 1.5T SONOS memory structure and a manufacturing method, comprises a P-well and a storage well on its side, gates of a select transistor and a storage transistor; the height of the select transistor gate is less than the height of the storage transistor gate, an stack layer is between the gats of the select transistor and the storage transistor which height is same as the storage transistor gate; the top of the select transistor gate has a first sidewall; the sidewall of the select transistor gate has a second sidewall. The present invention strengthens the isolation between the gates of the select transistor and the storage transistor, reduces the risk of current leakage, enables the metal silicide to also grow on the gate of the select transistor, reduces the resistance of the select transistor and improves the performance of the device. ## Claims ### Claim 1 A 1.5T SONOS memory structure, comprising: a P-type well and a storage well on one side of the P-type well; a select transistor gate on the P-type well; and a storage transistor gate on the storage well, wherein a height of the select transistor gate is less than a height of the storage transistor gate, a sidewall of the storage transistor gate farthest from the select transistor gate is a slope, and a first metal silicide is provided on the slope; an ONO stack layer is provided between the select transistor gate and the storage transistor gate, and a height of the ONO stack layer is the same as the height of the storage transistor gate; a top of the select transistor gate is provided with a first sidewall relying on the ONO stack layer; a remaining part of the top of the select transistor gate is provided with a second metal silicide; and a sidewall of the select transistor gate farthest from the storage transistor gate is provided with a second sidewall. ### Claim 2 (depends on 1) The 1.5T SONOS memory structure according to claim 1, wherein the P-type well and the storage well are located on a Deep N-type Well (DNW). ### Claim 3 (depends on 1) The 1.5T SONOS memory structure according to claim 1, wherein an upper surface of the storage well is provided with an implantation layer. ### Claim 4 (depends on 3) The 1.5T SONOS memory structure according to claim 3, wherein upper surfaces of the P-type well and the implantation layer are provided with an oxide layer. ### Claim 5 (depends on 4) The 1.5T SONOS memory structure according to claim 4, wherein the ONO stack layer is further provided between a bottom surface of the storage transistor gate and the oxide layer. ### Claim 6 (depends on 4) The 1.5T SONOS memory structure according to claim 4, wherein a third sidewall is provided on polysilicon between a lower end of the sidewall of the storage transistor gate and the oxide layer. ### Claim 7 (depends on 1) A method for manufacturing the 1.5T SONOS memory structure according to claim 1, wherein the method comprises: step 1: providing the P-type well and the storage well on the one side of the P-type well, depositing a polysilicon layer on the P-type well and the storage well, depositing silicon nitride on the polysilicon layer, and then performing photoetching and etching to form the select transistor gate on the P-type well and covered with a silicon nitride layer on the top; step 2: depositing the ONO stack layer on the P-type well, the select transistor gate, and the storage well; step 3: depositing polysilicon on the ONO stack layer, performing etching until the silicon nitride layer on the top of the select transistor gate is exposed, and forming the storage transistor gate on the storage well, the sidewall of the storage transistor gate farthest from the select transistor gate being the slope; step 4: performing photoetching to open adjacent storage units on the P-type well on the side of the select transistor gate farthest from the storage transistor gate, removing polysilicon on the adjacent storage units and a silicon oxide and silicon nitride layer on an outer layer of the ONO stack layer, and reserving a layer of silicon oxide on the sidewall of the select transistor gate and the adjacent storage units; step 5: removing the silicon nitride layer on the top of the select transistor gate, the height of the select transistor gate being less than the height of the storage transistor gate; step 6: sequentially performing deposition and etching to form the first sidewall relying on the ONO stack layer on the top of the select transistor gate and to form the second sidewall on the sidewall of the select transistor gate farthest from the storage transistor gate; and step 7: forming the second metal silicide on the remaining part of the top of the select transistor gate and the first metal silicide on the sidewall of the storage transistor gate. ### Claim 8 (depends on 7) The method for manufacturing the 1.5T SONOS memory structure according to claim 7, wherein in step 1, a thickness of the silicon nitride layer on the top of the select transistor gate formed after photoetching and etching is 500-600 angstroms. ### Claim 9 (depends on 7) The method for manufacturing the 1.5T SONOS memory structure according to claim 7, wherein in step 5, the silicon nitride layer on the top of the select transistor gate is removed through acid pickling. ### Claim 10 (depends on 7) The method for manufacturing the 1.5T SONOS memory structure according to claim 7, wherein in step 1, the P-type well and the storage well on the one side of the P-type well are located on a Deep N-type Well (DNW). ### Claim 11 (depends on 10) The method for manufacturing the 1.5T SONOS memory structure according to claim 10, wherein in step 1, an oxide layer is provided above the DNW and below the P-type well and the storage well. ### Claim 12 (depends on 11) The method for manufacturing the 1.5T SONOS memory structure according to claim 11, wherein in step 1, an implantation layer on the DNW is provided below the oxide layer on the storage well. ### Claim 13 (depends on 12) The method for manufacturing the 1.5T SONOS memory structure according to claim 12, wherein in step 6, deposition and etching are sequentially performed to form a third sidewall on the polysilicon between a lower end of the sidewall of the storage transistor gate and the oxide layer. ### Claim 14 (depends on 13) The method for manufacturing the 1.5T SONOS memory structure according to claim 13, wherein the first sidewall, the second sidewall, and the third sidewall are silicon nitride. ### Claim 15 (depends on 7) The method for manufacturing the 1.5T SONOS memory structure according to claim 7, wherein in step 7, the second metal silicide is formed on the remaining part of the top of the select transistor gate and the first metal silicide is formed on the sidewall of the storage transistor gate by adopting a self-alignment process.