# US 11,309,394 B2 · Semiconductor memory device, memory system, and defect detection method

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- Number: US 11,309,394 B2
- Document ID: US11309394B2
- Status: Granted
- Kind: B2
- Application number: 16/562,771
- Filed: 2019-09-06
- Published: 2020-08-13
- Granted: 2022-04-19
- Earliest claimed: 2019-02-13
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Shinya Haraguchi
- Web page: https://patentgrep.com/patent/US11309394B2

## CPC

- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/10: Programming or data input circuits
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/32: Timing circuits
- G11C 16/3445: {Circuits or methods to verify correct erasure of nonvolatile memory cells}
- G11C 29/006: {at wafer scale level, i.e. wafer scale integration [WSI]}
- G11C 29/025: {in signal lines}
- G11C 29/04: Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals}
- G11C 29/12005: {comprising voltage or current generators}
- G11C 29/18: Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G11C 29/50012: {of timing}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers}
- G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell}
- G11C 2029/0403: {during or with feedback to manufacture}
- G11C 2029/0411: {Online error correction}
- G11C 2029/1204: {Bit line control}
- G11C 2029/1806: {Address conversion or mapping, i.e. logical to physical address}
- G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information}
- G11C 2029/5004: {Voltage}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor memory device includes: a first wiring and a second wiring; a first selection transistor, a memory transistor, and a second selection transistor connected between the first wiring and the second wiring; and a third wiring and a fourth wiring connected to gate electrodes of the first selection transistor and the second selection transistor. From a first timing to a second timing, a first voltage that turns the first selection transistor ON is supplied to the third wiring, and a second voltage that turns the second selection transistor OFF is supplied to the fourth wiring. From the second timing to a third timing, a third voltage that turns the first selection transistor OFF is supplied to the third wiring, and at a fourth timing between the first timing and the third timing, at least one of a voltage and a current of the first wiring is detected.

## Claims

### Claim 1

A defect detection method for a semiconductor memory device, wherein the semiconductor memory device includes a first wiring and a second wiring, a memory transistor connected between the first wiring and the second wiring, a first selection transistor connected between the first wiring and the memory transistor, a second selection transistor connected between the second wiring and the memory transistor, a third wiring connected to a gate electrode of the first selection transistor, and a fourth wiring connected to a gate electrode of the second selection transistor, the defect detection method comprising:
from a first timing to a second timing, supplying a first voltage that turns the first selection transistor ON to the third wiring, and not supplying a second voltage that turns the first selection transistor OFF to the third wiring;
from the first timing to the second timing, not supplying a third voltage that turns the second selection transistor ON to the fourth wiring, and supplying a fourth voltage that turns the second selection transistor OFF to the fourth wiring;
from the second timing to a third timing, not supplying the first voltage to the third wiring, and supplying the second voltage to the third wiring; and
at a fourth timing between the first timing and the third timing, detecting at least one of a voltage and a current of the first wiring.

### Claim 2 (depends on 1)

The defect detection method for the semiconductor memory device according to claim 1, wherein
the semiconductor memory device includes a fifth wiring connected to a gate electrode of the memory transistor, and
the defect detection method further comprises supplying a potential difference to the first wiring and the fifth wiring at a predetermined timing between the first timing and the second timing.

### Claim 3 (depends on 1)

The defect detection method for the semiconductor memory device according to claim 1, wherein the semiconductor memory device further includes a sense transistor including a gate electrode connected to the first wiring, a latch circuit connected to the sense transistor, a switch transistor connected between the sense transistor and the latch circuit, and a sixth wiring connected to a gate electrode of the switch transistor, and
the defect detection method further comprises supplying a fifth voltage that turns the switch transistor ON to the sixth wiring at the fourth timing.

### Claim 4 (depends on 1)

The defect detection method for the semiconductor memory device according to claim 1, wherein the semiconductor memory device includes a plurality of the memory transistors connected between the first selection transistor and the second selection transistor, and a plurality of fifth wirings connected to respective gate electrodes of the plurality of memory transistors, and
the defect detection method further comprises supplying a sixth voltage to a plurality of the fifth wirings at a predetermined timing between the first timing and the second timing.

### Claim 5 (depends on 1)

The defect detection method for the semiconductor memory device according to claim 1, wherein the semiconductor memory device includes a plurality of the memory transistors connected between the first selection transistor and the second selection transistor, and a plurality of fifth wirings connected to respective gate electrodes of the plurality of memory transistors, and
the defect detection method further comprises:
supplying a seventh voltage to a plurality of the fifth wirings;
repeatedly performing a process that selects one of the fifth wirings from the plurality of fifth wirings, a process that switches a voltage of the selected fifth wiring to an eighth voltage different from the seventh voltage, and a process that detects at least one of a voltage and a current of the first wiring; and
outputting information configured to specify the fifth wiring corresponding to a timing at which the at least one of the voltage and the current of the first wiring detected has changed.

### Claim 6 (depends on 1)

The defect detection method for the semiconductor memory device according to claim 1, wherein the semiconductor memory device includes a plurality of the first wirings, a plurality of the memory transistors connected between the plurality of first wirings and the second wiring, a plurality of first selection transistors connected between the plurality of first wirings and the plurality of memory transistors, and a plurality of second selection transistors connected between the second wiring and the plurality of memory transistors,
the third wiring is commonly connected to gate electrodes of the plurality of first selection transistors,
the fourth wiring is commonly connected to gate electrodes of the plurality of second selection transistors,
the defect detection method further comprises detecting, at the fourth timing, at least one of voltages and currents of the plurality of first wirings, and
the defect detection method further comprises outputting information corresponding to the at least one of the voltages and the currents of the plurality of first wirings detected.