# US 11,309,387 B2 · Semiconductor device and method for fabricating the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,309,387 B2
- Document ID: US11309387B2
- Status: Granted
- Kind: B2
- Application number: 16/674,312
- Filed: 2019-11-05
- Published: 2021-05-06
- Granted: 2022-04-19
- Earliest claimed: 2019-11-05
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Tse-Yao Huang
- Web page: https://patentgrep.com/patent/US11309387B2

## CPC

- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties}
- H10D 84/835: {comprising LDMOS}
- H10W 90/00: Package configurations
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/014: {the gate conductors having different materials or different implants}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first semiconductor stack having a first threshold voltage and comprising a first insulating stack positioned on the substrate, a second semiconductor stack having a second threshold voltage and comprising a second insulating stack positioned on the substrate, and a third semiconductor stack having a third threshold voltage and comprising a third insulating stack positioned on the substrate. The first threshold voltage, the second threshold voltage, and the third threshold voltage are different from each other, a thickness of the first insulating stack is different from a thickness of the second insulating stack and a thickness of the third insulating stack, and the thickness of the second insulating stack is different from the thickness of the third insulating stack.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a first semiconductor stack having a first threshold voltage and comprising a first insulating stack positioned on the substrate;
a second semiconductor stack having a second threshold voltage and comprising a second insulating stack positioned on the substrate; and
a third semiconductor stack having a third threshold voltage and comprising a third insulating stack positioned on the substrate;
wherein the first threshold voltage, the second threshold voltage, and the third threshold voltage are different from each other; a thickness of the first insulating stack is different from a thickness of the second insulating stack and a thickness of the third insulating stack; and the thickness of the second insulating stack is different from the thickness of the third insulating stack;
wherein the first insulating stack comprises a first bottom insulating layer positioned on the substrate, and the third insulating stack comprises a third bottom insulating layer positioned on the substrate and a third top insulating layer positioned on the third bottom insulating layer;
wherein the second insulating stack comprises a second bottom insulating layer positioned on the substrate, a second middle insulating layer positioned on the second bottom insulating layer, and a second top insulating layer positioned on the second middle insulating layer;
wherein the second semiconductor stack further comprises a second bottom conductive layer positioned on the second top insulating layer; and
wherein the second semiconductor stack further comprises a second functional layer positioned between the second top insulating layer and the second bottom conductive layer, and the second functional layer has a thickness between about 10 angstroms and about 15 angstroms.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first semiconductor stack further comprises a first bottom conductive layer positioned on the first bottom insulating layer.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the first semiconductor stack further comprises a first top conductive layer positioned on the first bottom conductive layer.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the first semiconductor stack further comprises a first filler layer positioned on the first top conductive layer, and the first filler layer is formed of tungsten or aluminum.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the second semiconductor stack further comprises a second top conductive layer positioned on the second bottom conductive layer.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising a first pair of inner spacers attached to two sides of the first semiconductor stack.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, further comprising a first pair of outer spacers attached to outer surfaces of the first pair of inner spacers.

### Claim 8 (depends on 6)

The semiconductor device of claim 6, further comprising two first lightly-doped regions positioned adjacent to the first semiconductor stack and in the substrate.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, further comprising two first heavily-doped regions positioned adjacent to the first pair of inner spacers and in the substrate.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, further comprising a third pair of stress regions positioned adjacent to the third semiconductor stack, wherein lower portions of the third pair of stress regions are positioned in the substrate and upper portions of the third pair of stress regions protrude from a top surface of the substrate.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the second semiconductor stack further comprises a second dipole layer positioned between the substrate and the second bottom insulating layer, and the second dipole layer is formed of a material including one or more of lutetium oxide, lutetium silicon oxide, yttrium oxide, yttrium silicon oxide, lanthanum oxide, lanthanum silicon oxide, barium oxide, and barium silicon oxide.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein the second semiconductor stack further comprises a second protection layer positioned between the second top insulating layer and the second bottom conductive layer, and the second protection layer is formed of titanium nitride.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, wherein the second semiconductor stack further comprises a second encapsulation layer positioned between a second filler layer and the second bottom conductive layer, and the second encapsulation layer has a thickness between about 15 angstroms and about 25 angstroms.