# US 11,309,385 B2 · Strained nanowire CMOS device and method of forming

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- Number: US 11,309,385 B2
- Document ID: US11309385B2
- Status: Granted
- Kind: B2
- Application number: 16/939,726
- Filed: 2020-07-27
- Published: 2020-11-12
- Granted: 2022-04-19
- Earliest claimed: 2015-10-07
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Cheng-Yi Peng; Hung-Li Chiang; Yu-Lin Yang; Chih Chieh Yeh; Yee-Chia Yeo; Chi-Wen Liu
- Web page: https://patentgrep.com/patent/US11309385B2

## CPC

- H10D 62/121: {oriented parallel to substrates}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/0191: {forming stacked channels, e.g. changing their shapes or sizes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/503: {having non-rectangular cross-sections}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/853: {comprising FinFETs}
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10P 50/642: {Chemical etching}
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10P 50/242: {of Group IV materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate;
first source/drain regions and a first channel region interposed between the first source/drain regions over the substrate, the first source/drain regions and the first channel region comprising alternating layers of first epitaxial layers and second epitaxial layers, the first epitaxial layers and the second epitaxial layers extending continuously between the first source/drain regions;
second source/drain regions and a second channel region interposed between the second source/drain regions over the substrate, the second source/drain regions comprising alternating layers of the first epitaxial layers and the second epitaxial layers, wherein a bottommost layer of the first epitaxial layers of the first channel region is lower than a bottommost layer of the first epitaxial layers of the second channel region;
a first gate structure extending over the first channel region; and
a second gate structure extending over the second channel region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising an isolation region adjacent opposing sides of the first channel region and the second channel region, wherein an upper surface of the isolation region is recessed adjacent the second channel region.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein an upper surface of the isolation region is higher than a lower surface of the bottommost layer of the first epitaxial layers of the first channel region.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the substrate comprises a strain relaxation buffer over a semiconductor substrate.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the second gate structure extends completely between a bottommost layer of the second epitaxial layers of the second channel region and the substrate.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the bottommost layer of the first epitaxial layers of the first channel region extends from a bottommost layer of the second epitaxial layers of the first channel region to the substrate.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein sidewalls the first epitaxial layers of the first channel region and the second channel region are recessed from sidewalls of the second epitaxial layers of the first channel region and the second channel region, respectively.

### Claim 8

A semiconductor device comprising:
a substrate;
first source/drain regions and a first channel region interposed between the first source/drain regions, the first source/drain regions and the first channel region comprising alternating layers of first epitaxial layers and second epitaxial layers, the second epitaxial layers in the first channel region having a greater width than the first epitaxial layers in the first channel region in a direction perpendicular to current flow through the first channel region in a plan view;
second source/drain regions and a second channel region interposed between the second source/drain regions, the second source/drain regions and the second channel region comprising alternating layers of the first epitaxial layers and the second epitaxial layers, the second epitaxial layers in the second channel region having a greater width than the first epitaxial layers in the second channel region in a direction perpendicular to current flow through the second channel region in the plan view; and
a first gate structure extending over the first epitaxial layers and the second epitaxial layers in the first channel region, the first gate structure not extending completely between a bottommost layer of the second epitaxial layers of the first channel region and the substrate; and
a second gate structure extending over the first epitaxial layers and the second epitaxial layers in the second channel region, the second gate structure extending completely between a bottommost second epitaxial layer and the substrate.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, further comprising a dielectric layer over the substrate and adjacent the first channel region and the second channel region, the dielectric layer having a first thickness adjacent the first channel region and a second thickness adjacent the second channel region, the first thickness being different than the second thickness.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the first channel region is under a compressive stress.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein the first channel region and the second channel region have different conductivity types.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein sidewalls of the first epitaxial layers in the second channel region are linear in a cross-sectional view orthogonal to the current flow through the second channel region.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, wherein sidewalls of the first epitaxial layers in the second channel region are concave in a cross-sectional view orthogonal to the current flow through the second channel region.

### Claim 14

A semiconductor device comprising:
a substrate;
first source/drain regions and a first channel region interposed between the first source/drain regions over the substrate, the first source/drain regions and the first channel region comprising alternating layers of first epitaxial layers and second epitaxial layers, the first epitaxial layers and the second epitaxial layers extending continuously between the first source/drain regions;
second source/drain regions and a second channel region interposed between the second source/drain regions over the substrate, the second source/drain regions and the second channel region comprising alternating layers of the first epitaxial layers and the second epitaxial layers, wherein a bottommost layer of the first epitaxial layers of the first channel region is lower than a bottommost layer of the first epitaxial layers of the second channel region;
a first gate structure extending over the first channel region; and
a second gate structure extending over the second channel region, wherein the second gate structure extends completely around the second channel region.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, further comprising an isolation region adjacent opposing sides of the first channel region and the second channel region, wherein an upper surface of the isolation region is recessed adjacent the second channel region.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, wherein the second gate structure extends lower than the first gate structure.

### Claim 17 (depends on 14)

The semiconductor device of claim 14, wherein sidewalls of the first epitaxial layers in the second channel region are concave.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, wherein sidewalls of the second epitaxial layers in the first channel region are concave.

### Claim 19 (depends on 14)

The semiconductor device of claim 14, wherein the first channel region and the second channel region have different conductivity types.

### Claim 20 (depends on 14)

The semiconductor device of claim 14, wherein sidewalls of the second epitaxial layers in the second channel region are concave.