# US 11,309,384 B2 · Super junction semiconductor device and method of manufacturing the same

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- Number: US 11,309,384 B2
- Document ID: US11309384B2
- Status: Granted
- Kind: B2
- Application number: 16/804,794
- Filed: 2020-02-28
- Published: 2020-09-03
- Granted: 2022-04-19
- Earliest claimed: 2019-02-28
- Assignees: DB HiTek Co., Ltd.
- Applicants: Db Hitek Co., Ltd.
- Inventors: Young Seok Kim
- Web page: https://patentgrep.com/patent/US11309384B2

## CPC

- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 62/117: {Shapes of semiconductor bodies}
- H10D 64/01: Manufacture or treatment
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A super junction semiconductor device includes a substrate having a first conductive type, a blocking layer positioned on the substrate, the blocking layer including first conductive type pillars and second conductive type pillars, each extending in a vertical direction and arranging alternatively in a horizontal direction, and a gate structure disposed on the blocking layer, the gate structure extending in the horizontal direction and being electrically connected to ones of the first and second conductive type pillars. Thus, oscillation phenomena may be suppressed.

## Claims

### Claim 1

A super junction semiconductor device comprising:
a substrate having a first conductive type;
a blocking layer positioned on the substrate, the blocking layer including first conductive type pillars and second conductive type pillars, each extending in a vertical direction and arranged alternatively in a horizontal direction with respect to one another; and
a gate structure disposed on the blocking layer, the gate structure extending in the horizontal direction and electrically connected to ones of the first and second conductive type pillars,
wherein each pillar of ones of the first conductive type pillars and the second conductive type pillars includes a corresponding plurality of pillar cells stacked and overlapped with one another in the vertical direction such that the plurality of pillar cells of each pillar are electrically interconnected with one another, and each pillar cell has both a maximum width and overlapping widths along the horizontal direction,
wherein each of the second pillar cells has a spherical shape having a first diameter, and
wherein the overlapping width of each of the second conductive type cells is smaller than that of the second conductive type pillar cell above it.

### Claim 2 (depends on 1)

The super junction semiconductor device of claim 1, wherein each of the overlapping widths is in a range of 0.2 to 0.8 times the first diameter.

### Claim 3 (depends on 1)

The super junction semiconductor device of claim 1, wherein each of the second conductive type pillars has a bent sidewall arranged in contact with the first conductive type pillars adjacent to the second conductive type pillars.

### Claim 4 (depends on 1)

The super junction semiconductor device of claim 1, wherein the second conductive type pillars have shapes identical to each other with respect to one of the first conductive type pillars adjacent to the second conductive type pillars.

### Claim 5 (depends on 1)

The super junction semiconductor device of claim 1, wherein the gate structure includes:
a gate insulating layer extending in the horizontal direction to cross the first and the second conductive type pillars alternatively;
a gate electrode formed on the gate insulating layer; and
an insulating interlayer surrounding the gate electrode.

### Claim 6 (depends on 1)

The super junction semiconductor device of claim 1, further comprising p-body regions formed at top portions of the second conductive type pillars.

### Claim 7

A product made by the process of:
preparing a substrate of a first conductive type;
forming a blocking layer on the substrate, the blocking layer including first conductive type pillars and second conductive type pillars each extending in a vertical direction and arranged alternatively in a horizontal direction; and
forming a gate structure on the blocking layer, the gate structure extending in the horizontal direction and being electrically connected to one of the first and second conductive type pillars,
wherein each pillar of ones of the first conductive type pillars and the second conductive type pillars includes a corresponding plurality of pillar cells stacked and overlapped in the vertical direction and electrically interconnected to the other pillar cells of the same pillar, and wherein each pillar has a maximum width and an overlapping widths along the horizontal direction,
wherein forming the blocking layer comprises:
(a) forming a first epitaxial layer on the substrate;
(b) partially removing the first epitaxial layer to form a trench; and
(c) filling the trench to form a plurality of second pillar cells doped with second conductive type impurities to define a plurality of first pillar cells adjacent to the second pillar cells, and
(d) repeating (a) to (c),
wherein a second epitaxial layer formed on the first epitaxial layer and the first pillar cells has a thickness lower than that of the first epitaxial layer.

### Claim 8 (depends on 7)

The product made by the process of claim 7, wherein the trench has a spherical shape.

### Claim 9 (depends on 7)

The product made by the process of claim 7, wherein the trench has an overhang structure.

### Claim 10 (depends on 7)

The product made by the process of claim 7, wherein the each of the pillar cells has a spherical shape and defines a first diameter.

### Claim 11 (depends on 10)

The product made by the process of claim 10, wherein each of the overlapping widths is 0.2 to 0.8 times the first diameter D1.

### Claim 12 (depends on 7)

The product made by the process of claim 7, wherein the overlapping width of any given pillar cell is smaller than the overlapping width of the pillar cell above it.

### Claim 13

A product made by the process of:
preparing a substrate of a first conductive type;
forming a blocking layer on the substrate, the blocking layer including first conductive type pillars and second conductive type pillars each extending in a vertical direction and arranged alternatively in a horizontal direction; and
forming a gate structure on the blocking layer, the gate structure extending in the horizontal direction and being electrically connected to one of the first and second conductive type pillars,
wherein each pillar of ones of the first conductive type pillars and the second conductive type pillars includes a corresponding plurality of pillar cells stacked and overlapped in the vertical direction and electrically interconnected to the other pillar cells of the same pillar, and wherein each pillar has a maximum width and an overlapping widths along the horizontal direction,
wherein forming the blocking layer comprises:
(a) forming a first epitaxial layer on the substrate;
(b) implanting second conductive type impurities into the first epitaxial layer to form a first pillar cell of the second conductive type in the first epitaxial layer;
(c) forming a second epitaxial layer on the first epitaxial layer including the first pillar cells; and
(d) implanting second conductive type impurities into the second epitaxial layer to form a second pillar cell of the second conductive type, being connected with the first pillar cell, wherein the first epitaxial layer has a thickness larger than that of the second epitaxial layer.

### Claim 14 (depends on 13)

The product made by the process of claim 13, further comprising repeating (a) to (d).