# US 11,309,354 B2 · Three-dimensional nonvolatile memory device having resistance change structure and method of operating the same

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- Number: US 11,309,354 B2
- Document ID: US11309354B2
- Status: Granted
- Kind: B2
- Application number: 16/908,635
- Filed: 2020-06-22
- Published: 2021-07-01
- Granted: 2022-04-19
- Earliest claimed: 2019-12-30
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Jae Hyun Han; Se Ho Lee; Hyangkeun Yoo
- Web page: https://patentgrep.com/patent/US11309354B2

## CPC

- H10B 63/845: {the switching components being connected to a common vertical conductor}
- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0011: {comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]}
- G11C 13/003: {Cell access}
- G11C 13/0069: {Writing or programming circuits or methods}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/34: {of the vertical channel field-effect transistor type}
- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/245: {the species being metal cations, e.g. programmable metallization cells}
- H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices}
- H10N 70/8822: {Sulfides, e.g. CuS}
- H10N 70/8825: {Selenides, e.g. GeSe}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10N 70/8836: {Complex metal oxides, e.g. perovskites, spinels}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 2013/0071: {Write using write potential applied to access device gate}
- G11C 2213/53: Structure wherein the resistive material being in a transistor, e.g. gate
- G11C 2213/71: Three dimensional array
- G11C 2213/75: Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
- G11C 2213/79: Array wherein the access device being a transistor
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A nonvolatile memory device includes a substrate having an upper surface and a channel structure disposed over the substrate. The channel structure includes at least one channel layer pattern and at least one interlayer insulation layer pattern, which are alternately stacked in a first direction perpendicular to the upper surface, and the channel structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a resistance change layer disposed over the substrate and on at least a portion of one sidewall surface of the channel structure, a gate insulation layer disposed over the substrate and on the resistance change layer, and a plurality of gate line structures disposed over the substrate, each contacting a first surface of the gate insulation layer and disposed to be spaced apart from each other in the second direction.

## Claims

### Claim 1

A nonvolatile memory device comprising:
a substrate having an upper surface;
a channel structure disposed over the substrate, the channel structure comprising at least one channel layer pattern and at least one interlayer insulation layer pattern, which are alternately stacked in a first direction perpendicular to the upper surface, wherein the channel structure extends in a second direction perpendicular to the first direction;
a resistance change layer disposed over the substrate and on at least a portion of one sidewall surface of the channel structure;
a gate insulation layer disposed over the substrate and on the resistance change layer; and
a plurality of gate line structures disposed over the substrate, each contacting a first surface of the gate insulation layer,
wherein each of the plurality of gate line structures is disposed to be spaced apart from each other in the second direction.

### Claim 2 (depends on 1)

The nonvolatile memory device of claim 1, wherein each of the plurality of gate line structures is disposed to overlap portions of the resistance change layer that correspond to the at least one channel layer pattern in a third direction perpendicular to the first and the second direction.

### Claim 3 (depends on 1)

The nonvolatile memory device of claim 1, wherein each of the plurality of gate line structures has a pillar shape.

### Claim 4 (depends on 1)

The nonvolatile memory device of claim 1, wherein the resistance change layer comprises an oxide having oxygen vacancies, and
wherein the oxide is at least one oxide selected from the group consisting of titanium oxide, aluminum oxide, nickel oxide, copper oxide, zirconium oxide, manganese oxide, hafnium oxide, tungsten oxide, tantalum oxide, niobium oxide, and iron oxide.

### Claim 5 (depends on 1)

The nonvolatile memory device of claim 1, wherein the resistance change layer comprises at least one selected from the group consisting of PCMO (Pr1-xCaxMnO3, 0<x<1), LCMO (La1-xCaxMnO3, 0<x<1), BSCFO (Ba0.5Sr0.5Co0.8Fe0.2O3-δ), YBCO (YBa2Cu3O7-x, 0<x<1), (Ba, Sr)TiO3 doped with chromium (Cr) or niobium (Nb), SrZrO3 doped with chromium (Cr) or vanadium (V), (La, Sr) MnO3, Sr1-xLaxTiO3 (0<x<1), La1-xSrxFeO3 (0<x<1), La1-xSrxCoO3 (0<x<1), SrFeO2.7, LaCoO3, RuSr2GdCu2O3, and YBa2Cu3O7.

### Claim 6 (depends on 1)

The nonvolatile memory device of claim 1, wherein the resistance change layer comprises at least one selected from the group consisting of germanium-antimony-tellurium (GST), arsenic-antimony-tellurium (As—Sb—Te), tin-antimony-tellurium (Sn—Sb—Te), tin-indium-antimony-tellurium (Sn—In—Sb—Te), arsenic-germanium-antimony-tellurium (As—Ge—Sb—Te), GexSe1-x (0<x<1), silver sulfide (Ag2S), copper sulfide (Cu2S), Cadmium sulfide (CdS), zinc sulfide (ZnS), and selenium oxide (CeO2).

### Claim 7 (depends on 1)

The nonvolatile memory device of claim 1, wherein the channel layer comprises a semiconductor material or a metal oxide.

### Claim 8 (depends on 1)

The nonvolatile memory device of claim 1, wherein the resistance change layer is disposed to cover a sidewall surface of the channel layer pattern and a sidewall surface of the interlayer insulation layer pattern.

### Claim 9 (depends on 1)

The nonvolatile memory device of claim 1, further comprising a plurality of insulation structures disposed over the substrate and arranged to alternate with the plurality of gate line structures along the second direction, the plurality of insulation structures extending in the first direction.

### Claim 10 (depends on 9)

The nonvolatile memory device of claim 9, wherein each of the plurality of insulation structures is disposed to contact the channel structure in a third direction perpendicular to the first and second directions and is disposed to contact the plurality of gate line structures, the resistance change layer and the gate insulation layer in the second direction.

### Claim 11 (depends on 9)

The nonvolatile memory device of claim 9, wherein the channel layer pattern of the channel structure contacts the resistance change layer in the third direction, and the interlayer insulation layer pattern of the channel structure contacts the plurality of gate line structures and the plurality of insulation structures in the third direction.

### Claim 12

A nonvolatile memory device comprising:
a substrate having an upper surface;
a first channel structure and a second channel structure disposed over the substrate, each comprising at least one channel layer pattern and at least one interlayer insulation layer pattern, which are alternately stacked in a first direction perpendicular to the upper surface, and each extending in a second direction perpendicular to the first direction, wherein the first channel structure and the second channel structure are spaced apart from each other in a third direction perpendicular to the first and second directions;
a first resistance change layer and a first gate insulation layer sequentially disposed on a sidewall surface of the first channel structure along the third direction;
a second resistance change layer and a second gate insulation layer sequentially disposed on a sidewall surface of the second channel structure along the third direction; and
a plurality of gate line structures disposed over the substrate and disposed between the first channel structure and the second channel structure and extending in the first direction,
wherein each of the plurality of gate line structures is spaced apart from each other along the second direction.

### Claim 13 (depends on 12)

The nonvolatile memory device of claim 12, wherein each of the plurality of gate line structures is disposed to electrically cover portions of the resistance change layer that correspond to the at least one channel layer pattern.

### Claim 14 (depends on 12)

The nonvolatile memory device of claim 12, wherein each of the plurality of gate line structures has a pillar shape.

### Claim 15 (depends on 12)

The nonvolatile memory device of claim 12, further comprising a plurality of insulation structures disposed over the substrate and arranged to alternate with the plurality of gate line structures along the second direction, the plurality of insulation structures extending in the first direction.

### Claim 16 (depends on 15)

The nonvolatile memory device of claim 15, wherein each of the plurality of insulation structures is disposed to contact the channel structure in a third direction perpendicular to the first and second directions, and is disposed to contact the plurality of gate line structures, the first and second resistance change layers, and the first and second gate insulation layers in the second direction.

### Claim 17 (depends on 15)

The nonvolatile memory device of claim 15, wherein the channel layer patterns of the first and second channel structures contact the first and second resistance change layers, respectively, in the third direction, and the interlayer insulation layer patterns of the first and second channel structure contact the gate line structures and the insulation structure in the third direction.