# US 11,309,353 B2 · Spacer-defined back-end transistor as memory selector

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- Number: US 11,309,353 B2
- Document ID: US11309353B2
- Status: Granted
- Kind: B2
- Application number: 17/078,583
- Filed: 2020-10-23
- Published: 2021-11-04
- Granted: 2022-04-19
- Earliest claimed: 2020-04-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Ken-Ichi Goto; Chung-Te Lin; Mauricio Manfrini
- Web page: https://patentgrep.com/patent/US11309353B2

## CPC

- H10B 61/22: {of the field-effect transistor [FET] type}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 50/01: Manufacture or treatment
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device comprises a substrate and an interconnect structure disposed over the substrate. The interconnect structure comprises stacked interconnect metal layers disposed within stacked interlayer dielectric (ILD) layers. A memory cell is disposed between an upper interconnect metal layer and an intermediate interconnect metal layer. A selecting transistor is connected to the memory cell and disposed between the intermediate interconnect metal layer and a lower interconnect metal layer. By placing the selecting transistor within the back-end interconnect structure between two interconnect metal layers, front-end space is saved, and more integration flexibility is provided.

## Claims

### Claim 1

A memory device, comprising:
a substrate;
an interconnect structure disposed over the substrate, the interconnect structure comprising stacked interconnect metal layers disposed within stacked interlayer dielectric (ILD) layers, the stacked interconnect metal layers comprising a lower interconnect metal layer, an intermediate interconnect metal layer, and an upper interconnect metal layer one disposed over another;
a memory cell disposed between the upper interconnect metal layer and the intermediate interconnect metal layer; and
a selecting transistor connected to the memory cell and disposed between the intermediate interconnect metal layer and the lower interconnect metal layer.

### Claim 2 (depends on 1)

The memory device of claim 1, the selecting transistor comprising:
a selector channel layer;
a first selector source/drain region and a second selector source/drain region disposed on the selector channel layer; and
a sidewall spacer disposed between and separating the first selector source/drain region and the second selector source/drain region.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the selecting transistor comprises a selector gate electrode and a selector gate dielectric disposed between the lower interconnect metal layer and the selector channel layer.

### Claim 4 (depends on 2)

The memory device of claim 2, wherein the sidewall spacer has a ring shape and encloses the second selector source/drain region.

### Claim 5 (depends on 2)

The memory device of claim 2, wherein the second selector source/drain region has a round or oval shape from a top view.

### Claim 6 (depends on 2)

The memory device of claim 2, wherein the second selector source/drain region has a square or rectangular shape from a top view and is surrounded by the first selector source/drain region.

### Claim 7 (depends on 2)

The memory device of claim 2, wherein the second selector source/drain region is connected to the intermediate interconnect metal layer.

### Claim 8 (depends on 2)

The memory device of claim 2, wherein the selector channel layer comprises oxide semiconductor material.

### Claim 9 (depends on 2)

The memory device of claim 2, wherein the selector channel layer is made of indium gallium zinc oxide (IGZO).

### Claim 10 (depends on 1)

The memory device of claim 1, wherein the memory cell comprises a bottom electrode disposed on the intermediate interconnect metal layer, a data storage structure disposed over the bottom electrode, and a top electrode disposed over the data storage structure.

### Claim 11

A memory device, comprising:
a substrate;
an interconnect structure disposed over the substrate, the interconnect structure comprising a plurality of interconnect metal layers one stacked over another and disposed in an interlayer dielectric (ILD) layer;
a plurality of memory cells disposed within the interconnect structure and arranged in an array of rows and columns; and
a plurality of selecting transistors correspondingly connected to the plurality of memory cells, wherein the plurality of selecting transistors is disposed within the interconnect structure between a lower interconnect metal layer and an upper interconnect metal layer of the interconnect structure.

### Claim 12 (depends on 11)

The memory device of claim 11, wherein the plurality of memory cells respectively comprises:
a bottom electrode;
a data storage structure disposed over the bottom electrode; and
a top electrode disposed over the data storage structure;
wherein a row of the memory cells shares a common bit line connecting to the top electrodes of the row of the memory cells.

### Claim 13 (depends on 12)

The memory device of claim 12,
wherein the row of the selecting transistors shares a common first selector source/drain region and respectively has an individual second selector source/drain region; and
wherein the individual second selector source/drain regions are islands surrounded by the common first selector source/drain region.

### Claim 14 (depends on 13)

The memory device of claim 13, wherein the individual second selector source/drain regions respectively connect to the corresponding bottom electrode.

### Claim 15 (depends on 13)

The memory device of claim 13, wherein the individual second selector source/drain region is separated from the common first selector source/drain region by a sidewall spacer.

### Claim 16 (depends on 15)

The memory device of claim 15, further comprising a selector channel layer disposed under the common first selector source/drain region, the individual second selector source/drain region, and the sidewall spacer.

### Claim 17 (depends on 11)

The memory device of claim 11, wherein a column of the selecting transistors shares a common gate electrode or has individual gate electrodes connecting to a common word line.

### Claim 18

A method of manufacturing a memory device, the method comprising:
forming a lower interconnect metal layer over a substrate and surrounded by a lower interlayer dielectric (ILD) layer;
forming a plurality of selecting transistors on the lower interconnect metal layer;
forming an intermediate interconnect metal layer on the plurality of selecting transistors;
forming a plurality of memory cells on the intermediate interconnect metal layer; and
forming an upper interconnect metal layer on the plurality of memory cells.

### Claim 19 (depends on 18)

The method of claim 18, wherein forming a selecting transistor of the plurality of selecting transistors comprises:
forming a selector gate electrode within the lower ILD layer;
forming a selector channel layer over the selector gate electrode and the lower ILD layer;
forming a first selector source/drain region and a second selector source/drain region on the selector channel layer; and
forming the intermediate interconnect metal layer on the second selector source/drain region.

### Claim 20 (depends on 19)

The method of claim 19, wherein forming the first selector source/drain region and the second selector source/drain region comprises:
forming a first selector source/drain layer on the selector channel layer;
forming a trench through the first selector source/drain layer;
forming a sidewall spacer along a sidewall of the trench; and
filling the second selector source/drain region in the trench.