# US 11,309,334 B2 · Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells

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- Number: US 11,309,334 B2
- Document ID: US11309334B2
- Status: Granted
- Kind: B2
- Application number: 17/100,937
- Filed: 2020-11-22
- Published: 2021-04-08
- Granted: 2022-04-19
- Earliest claimed: 2018-09-11
- Assignees: iCometrue Company Ltd.
- Applicants: Cometrue Company Ltd.
- Inventors: Mou-Shiung Lin; Jin-Yuan Lee
- Web page: https://patentgrep.com/patent/US11309334B2

## CPC

- H10D 84/907: {CMOS gate arrays}
- G06N 3/065: Analogue means
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 11/1675: {Writing or programming circuits or methods}
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 14/0036: {and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell}
- H01F 10/329: {Spin-exchange coupled multilayers wherein the magnetisation of the free layer is switched by a spin-polarised current, e.g. spin torque effect}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10B 63/22: {of the metal-insulator-metal type}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10W 40/28: comprising Peltier coolers
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 14/0081: {and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell}
- H01F 10/3254: {the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ]}
- H03K 19/17744: {for input/output signals}
- H10B 10/18: {Peripheral circuit regions}
- H10D 84/938: {Implementation of memory functions}
- H10D 84/975: {Wiring regions or routing}
- H10N 10/17: characterised by the structure or configuration of the cell or thermocouple forming the device
- H10N 10/817: the junction being non-separable, e.g. being cemented, sintered or soldered
- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/07254: {changes in dispositions}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07354: {changes in dispositions}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/225: {Bumps having a filler embedded in a matrix}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/253: {not comprising solid metals or solid metalloids, e.g. polymers or ceramics}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/00: Package configurations
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H01F: MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC chip is configured to pass data associated with the output data for the logic operation to the second IC chip through the interposer.

## Claims

### Claim 1

A semiconductor integrated-circuit (IC) chip comprising:
a non-volatile memory (NVM) cell for storing configuration data therein, wherein the non-volatile memory (NVM) cell comprises a first spin-orbit-torque-based (SOT-based) magnetoresistive-random-access-memory (MRAM) cell therein comprising a metal layer, a first magnetic layer, an oxide layer between the metal layer and first magnetic layer, and a second magnetic layer between the metal layer and oxide layer and in contact with the metal layer, wherein the metal layer has a first node and a second node and is configured for an electric current flowing along a horizontal direction from the first node to the second node through the metal layer;
a switch having first data at an input point thereof, wherein the first data is associated with the configuration data;
a first interconnect coupling to the configurable switch; and
a second interconnect coupling to the switch, wherein the switch is configured to control, in accordance with the first data, coupling between the first and second interconnects.

### Claim 2 (depends on 1)

The semiconductor integrated-circuit (IC) chip of claim 1, wherein the metal layer comprises platinum.

### Claim 3 (depends on 1)

The semiconductor integrated-circuit (IC) chip of claim 1, wherein the metal layer comprises tantalum.

### Claim 4 (depends on 1)

The semiconductor integrated-circuit (IC) chip of claim 1, wherein the metal layer comprises tungsten.

### Claim 5 (depends on 1)

The semiconductor integrated-circuit (IC) chip of claim 1, wherein the first spin-orbit-torque-based (SOT-based) magnetoresistive-random-access-memory (MRAM) cell has a third node coupling to the first node through, in sequence, the first magnetic layer, oxide layer, second magnetic layer and metal layer, and the third node couples to the second node through, in sequence, the first magnetic layer, oxide layer, second magnetic layer and metal layer.

### Claim 6 (depends on 1)

The semiconductor integrated-circuit (IC) chip of claim 1, wherein the oxide layer comprises magnesium oxide.

### Claim 7 (depends on 1)

The semiconductor integrated-circuit (IC) chip of claim 1, wherein the first magnetic layer comprises cobalt, iron and boron.

### Claim 8 (depends on 1)

The semiconductor integrated-circuit (IC) chip of claim 1, wherein the first spin-orbit-torque-based (SOT-based) magnetoresistive-random-access-memory (MRAM) cell further comprises an antiferromagnetic layer therein, wherein the first magnetic layer is between the oxide layer and antiferromagnetic layer.

### Claim 9 (depends on 1)

The semiconductor integrated-circuit (IC) chip of claim 1, wherein the non-volatile memory (NVM) cell further comprises a second spin-orbit-torque-based (SOT-based) magnetoresistive-random-access-memory (MRAM) cell therein coupling to the first spin-orbit-torque-based (SOT-based) magnetoresistive-random-access-memory (MRAM) cell.

### Claim 10 (depends on 1)

The semiconductor integrated-circuit (IC) chip of claim 1 is a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.

### Claim 11 (depends on 1)

The semiconductor integrated-circuit (IC) chip of claim 1 further comprising a data latch circuit for storing second data therein associated with the configuration data, wherein the first data is associated with the second data.

### Claim 12 (depends on 11)

The semiconductor integrated-circuit (IC) chip of claim 11, wherein the data latch circuit comprises a static-random-access memory (SRAM) cell.

### Claim 13 (depends on 1)

The semiconductor integrated-circuit (IC) chip of claim 1 further comprising a sense amplifier for generating second data at an output point thereof by sensing third data at an input point thereof associated with the configuration data, wherein the first data is associated with the second data.

### Claim 14 (depends on 13)

The semiconductor integrated-circuit (IC) chip of claim 13 further comprising a static-random-access memory (SRAM) cell for storing fourth data therein associated with the second data, wherein the first data is associated with the fourth data.

### Claim 15

A semiconductor integrated-circuit (IC) chip comprising:
a non-volatile memory (NVM) cell for storing therein a resulting value of a look-up table (LUT) for logic operation, wherein a spin-orbit-torque-based (SOT-based) magnetoresistive-random-access-memory (MRAM) cell of the non-volatile memory (NVM) cell comprises a metal layer, a first magnetic layer, an oxide layer between the metal layer and first magnetic layer, and a second magnetic layer between the metal layer and oxide layer and in contact with the metal layer, wherein the metal layer has a first node and a second node and is configured for an electric current flowing along a horizontal direction from the first node to the second node through the metal layer; and
a selection circuit to be configured in accordance with a first input data set having data associated with the resulting value.

### Claim 16 (depends on 15)

The semiconductor integrated-circuit (IC) chip of claim 15, wherein the metal layer comprises platinum.

### Claim 17 (depends on 15)

The semiconductor integrated-circuit (IC) chip of claim 15, wherein the metal layer comprises tantalum.

### Claim 18 (depends on 15)

The semiconductor integrated-circuit (IC) chip of claim 15, wherein the metal layer comprises tungsten.

### Claim 19 (depends on 15)

The semiconductor integrated-circuit (IC) chip of claim 15, wherein the spin-orbit-torque-based (SOT-based) magnetoresistive-random-access-memory (MRAM) cell has a third node coupling to the first node through, in sequence, the first magnetic layer, oxide layer, second magnetic layer and metal layer, and the third node couples to the second node through, in sequence, the first magnetic layer, oxide layer, second magnetic layer and metal layer.

### Claim 20 (depends on 15)

The semiconductor integrated-circuit (IC) chip of claim 15, wherein the oxide layer comprises magnesium oxide.

### Claim 21 (depends on 15)

The semiconductor integrated-circuit (IC) chip of claim 15, wherein the first magnetic layer comprises cobalt, iron and boron.

### Claim 22 (depends on 15)

The semiconductor integrated-circuit (IC) chip of claim 15, wherein the spin-orbit-torque-based (SOT-based) magnetoresistive-random-access-memory (MRAM) cell further comprises an antiferromagnetic layer therein, wherein the first magnetic layer is between the oxide layer and antiferromagnetic layer.

### Claim 23 (depends on 15)

The semiconductor integrated-circuit (IC) chip of claim 15 is a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.

### Claim 24 (depends on 15)

The semiconductor integrated-circuit (IC) chip of claim 15, wherein the selection circuit comprises a first set of input points for the first input data set and a second set of input points for a second input data set for the logic operation, wherein the selection circuit is configured to select, in accordance with the second input data set, input data from the first input data set as output data for the logic operation.