# US 11,309,333 B2 · Semiconductor integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,333 B2 - Document ID: US11309333B2 - Status: Granted - Kind: B2 - Application number: 16/997,878 - Filed: 2020-08-19 - Published: 2021-06-24 - Granted: 2022-04-19 - Earliest claimed: 2019-12-24 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Muneaki Maeno - Web page: https://patentgrep.com/patent/US11309333B2 ## CPC - H10D 84/907: {CMOS gate arrays} - H10D 89/811: {using FETs as protective elements} - H10D 89/814: {involving a parasitic bipolar transistor triggered by the electrical biasing of the gate electrode of the FET, e.g. gate coupled transistors} - H10D 84/924: {for current drive capability} - H10D 84/966: {Gate electrode terminals or contacts} - H10D 84/981: {Power supply lines} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor integrated circuit includes a first power line to which a first voltage is continuously applied, a second power line, a power switch cell connected to the first power line and configured to output a second voltage to the second power line according to a first signal, a logic circuit driven by the second voltage applied via the second power line, a first circuit driven by the second voltage applied via the second power line and configured to output a third voltage to logic circuit according to a second signal which is an inverted signal of the first signal, and a second circuit driven by the second voltage applied via the second power line and configured to output a fourth voltage to logic circuit according to a third signal which is an inverted signal of the second signal, the fourth voltage being lower than the third voltage. ## Claims ### Claim 1 A semiconductor integrated circuit, comprising: a first power line to which a first voltage is applied; a second power line; a first power switch cell connected to the first power line and configured to output a second voltage to the second power line according to a first signal; a first logic circuit driven by the second voltage applied via the second power line; a first circuit driven by the second voltage applied via the second power line and configured to output a third voltage to first logic circuit according to a second signal which is an inverted signal of the first signal; and a second circuit driven by the second voltage applied via the second power line and configured to output a fourth voltage to first logic circuit according to a third signal which is an inverted signal of the second signal, the fourth voltage being lower than the third voltage. ### Claim 2 (depends on 1) The semiconductor integrated circuit according to claim 1, wherein the first circuit includes: an N-type metal-oxide semiconductor field-effect transistor (NMOSFET) having a source terminal connected to a third power line, and a gate terminal and a drain terminal which are short-circuited with each other; and a P-type metal-oxide semiconductor field-effect transistor (PMOSFET) having: a source terminal connected to the second power line, a gate terminal connected to the gate terminal of the NMOSFET and to which the second signal is input, and a drain terminal from which the third voltage is output. ### Claim 3 (depends on 2) The semiconductor integrated circuit according to claim 2, further comprising: a first branch line to which the second signal is supplied, wherein the first branch line is connected to the gate terminal of each of the NMOSFET and the PMOSFET. ### Claim 4 (depends on 1) The semiconductor integrated circuit according to claim 1, wherein the second circuit includes: a P-type metal-oxide semiconductor field-effect transistor (PMOSFET) having a source terminal connected to the second power line, and a gate terminal and a drain terminal which are short-circuited with each other; and an N-type metal-oxide semiconductor field-effect transistor (NMOSFET) having: a source terminal connected to a third power line, a gate terminal connected to the gate terminal of the PMOSFET and to which the third signal is supplied, and a drain terminal from which the fourth voltage is output. ### Claim 5 (depends on 4) The semiconductor integrated circuit according to claim 4, further comprising: a second branch line to which the third signal is supplied, wherein the second branch line is connected to the gate terminal of each of the NMOSFET and the PMOSFET. ### Claim 6 (depends on 1) The semiconductor integrated circuit according to claim 1, wherein the first power switch cell includes: a first inverter gate configured to invert the first signal to output the second signal; a second inverter gate connected to invert the second signal to output the third signal; and a switch disposed between the first and second power lines and configured to output the second voltage to the second power line according to the second signal. ### Claim 7 (depends on 6) The semiconductor integrated circuit according to claim 6, wherein the switch includes a P-type metal-oxide semiconductor field-effect transistor (PMOSFET). ### Claim 8 (depends on 1) The semiconductor integrated circuit according to claim 1, wherein a threshold voltage of a transistor of the first power switch cell is higher than a threshold voltage of a transistor of any of the first logic circuit, the first circuit, and the second circuit. ### Claim 9 (depends on 1) The semiconductor integrated circuit according to claim 1, further comprising: a first region to which the first voltage is continuously applied via the first power line; and a second region to which the second voltage is applied via the second power line, wherein the first and second circuits are included in the second region. ### Claim 10 (depends on 9) The semiconductor integrated circuit according to claim 9, wherein the first power switch cell is included in the second region. ### Claim 11 (depends on 1) The semiconductor integrated circuit according to claim 1, further comprising: a second logic circuit driven by the second voltage; a third circuit driven by the second voltage and configured to output the third voltage to the second logic circuit according to the second signal; and a fourth circuit driven by the second voltage and configured to output the fourth voltage to the second logic circuit according to the third signal. ### Claim 12 (depends on 11) The semiconductor integrated circuit according to claim 11, further comprising: a first region to which the first voltage is continuously applied via the first power line; a second region to which the second voltage is applied via the second power line; and a second power switch cell connected to the first power line and configured to output the second voltage to the second power line, wherein at least one of the first and second power switch cells is included in the second region. ### Claim 13 A semiconductor integrated circuit, comprising: a first power line; a second power line; a first signal line; a first inverter connected to the first power line and having input and output electrodes, the input electrode connected to the first signal line; a first switch having gate, source, and drain electrodes, wherein the gate electrode is connected to the output electrode of the first inverter, one of the source and drain electrodes is connected to the first power line, and the other of the source and drain electrodes is connected to the second power line; a second inverter having input and output electrodes, the input electrode thereof connected to the output electrode of the first inverter; and a first circuit connected to the second power line and having first and second input electrodes, wherein the first input electrode is connected to the output electrode of the first inverter, and the second input electrode is connected to the output electrode of the second inverter. ### Claim 14 (depends on 13) The semiconductor integrated circuit according to claim 13, wherein the first inverter is configured to invert a first signal that is input through the first signal line to generate a second signal, the second inverter is configured to invert the second signal to generate a third signal, and a voltage level of the second signal is less than the third signal. ### Claim 15 (depends on 14) The semiconductor integrated circuit according to claim 14, further comprising: a first buffer gate between the output electrode of the first inverter and the first input electrode of the first circuit, and a second buffer gate between the output electrode of the second inverter and the second input electrode of the first circuit. ### Claim 16 (depends on 14) The semiconductor integrated circuit according to claim 14, wherein a first voltage is continuously applied to the first power line, and the first switch is configured to output a second voltage to the second power line according to the second signal. ### Claim 17 (depends on 13) The semiconductor integrated circuit according to claim 13, wherein the first switch is a transistor having a threshold voltage higher than a threshold voltage of a transistor of the first circuit. ### Claim 18 (depends on 13) The semiconductor integrated circuit according to claim 13, further comprising: a second circuit driven by the second voltage. ### Claim 19 (depends on 18) The semiconductor integrated circuit according to claim 18, further comprising: a first region to which a first voltage is continuously applied via the first power line; a second region to which a second voltage is applied via the second power line; and a second switch connected to the first power line and configured to apply the second voltage to the second power line, wherein at least one of the first and second switches is included in the second region.