# US 11,309,331 B2 · 3-dimensional NOR memory array architecture and methods for fabrication thereof

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- Number: US 11,309,331 B2
- Document ID: US11309331B2
- Status: Granted
- Kind: B2
- Application number: 17/011,836
- Filed: 2020-09-03
- Published: 2020-12-24
- Granted: 2022-04-19
- Earliest claimed: 2017-06-20
- Assignees: Sunrise Memory Corporation
- Applicants: Sunrise Memory Corporation
- Inventors: Eli Harari; Scott Brad Herner; Wu-Yi Henry Chien
- Web page: https://patentgrep.com/patent/US11309331B2

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/46: comprising air gaps
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- H10P 50/283: {by chemical means}
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method addresses low cost, low resistance metal interconnects and mechanical stability in a high aspect ratio structure. According to the various implementations disclosed herein, a replacement metal process, which defers the need for a metal etching step in the fabrication process until after all patterned photoresist is no longer present. Under this process, the conductive sublayers may be both thick and numerous. The present invention also provides for a strut structure which facilitates etching steps on high aspect ratio structures, which enhances mechanical stability in a high aspect ratio memory stack.

## Claims

### Claim 1

A memory structure, comprising:
a semiconductor substrate having a substantially planar surface;
a first stack of active strips and a second stack of active strips formed over the surface of the semiconductor substrate and separated by a predetermined distance along a first direction substantially parallel the planar surface, wherein each stack of active strips comprises two or more active strips provided one on top of another, with adjacent active strips being isolated from each other by a first dielectric layer, the active strips being substantially aligned lengthwise with each other along a second direction that is substantially also parallel to the planar surface but orthogonal the first direction, and wherein each active strip comprises a first semiconductor layer of a first conductivity type provided in one or more recessed portions of a second dielectric layer sandwiched between a second semiconductor layer and a third semiconductor layer each of a second conductivity type, the first, second and third semiconductor layers being stacked along a third direction that is substantially normal to the planar surface;
a storage layer; and
a plurality of conductors each extending lengthwise along the third direction, each conductor being within a group of the conductors that are provided between the first stack of active strips and the second stack of active strips and separated from each stack of active strips by the storage layer, thereby forming in each active strip at least one NOR string, each NOR string including a plurality of storage transistors that are formed out of the first, the second and the third semiconductor layers of the active strip and their adjacent the storage layer and the conductors within the group.

### Claim 2 (depends on 1)

The memory structure of claim 1, wherein each active strip further comprises at least one metallic layer that is in electrical contact with, and in substantial alignment lengthwise with, one of: the second semiconductor layer and the third semiconductor layer.

### Claim 3 (depends on 1)

The memory structure of claim 1, further comprising a metallic layer contacting one of the second and the third semiconductor layer.

### Claim 4 (depends on 3)

The memory structure of claim 3, further comprising:
a layer of non-conductive material provided between the second semiconductor layer and the first dielectric layer; and
a metallic layer that is provided in cavities or recesses formed in the non-conductive layer, the metallic being in electrical contact with the second semiconductor layer.

### Claim 5 (depends on 1)

The memory structure of claim 1 wherein the non-conductive layer comprises one or more of: silicon oxide, boron doped silicon oxide, phosphorus doped silicon oxide, boron phosphorus doped silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon oxygen hydrogen, germanium, and any combinations thereof.

### Claim 6 (depends on 4)

The memory structure of claim 4 wherein the non-conductive layer is porous.

### Claim 7 (depends on 3)

The memory structure of claim 3, wherein the metallic layer further comprises two or more sublayers where a first sublayer is disposed adjacent to and in electrical contact with a second sublayer, and the first sublayer surrounds the second sublayer on three or more sides.

### Claim 8 (depends on 7)

The memory structure of claim 7 wherein the thickness of the second sublayer is at least 1.5× the thickness of the first sublayer.

### Claim 9 (depends on 3)

The memory structure of claim 3, wherein the metallic layer comprises one or more of: titanium, titanium nitride, tungsten nitride, tungsten, titanium tungsten, tantalum, tantalum nitride, cobalt, chrome, molybdenum, niobium, and any alloys thereof.

### Claim 10 (depends on 3)

The memory structure of claim 3, wherein the metallic layer is deposited by atomic layer deposition.

### Claim 11 (depends on 1)

The memory structure of claim 1, further comprising a hard mask layer that includes one or more struts formed between two adjacent stacks of active strips, wherein each strut comprises an insulating layer physically connecting the adjacent stacks of active strips.

### Claim 12 (depends on 11)

The memory structure of claim 11, wherein the strut is in contact with and disposed to adjacent stacks of active strips at only a portion of the height of one of the stacks of active strips.

### Claim 13 (depends on 11)

The memory structure of claim 11, wherein each struct connects adjacent stacks of active strips at the top of the stacks.

### Claim 14 (depends on 11)

The memory structure of claim 11, wherein each strut is in contact with and disposed to adjacent stacks of active strips along substantially the entire height of the memory structure.

### Claim 15 (depends on 1)

The memory structure of claim 1, wherein the storage layer in the memory structure comprises first and second types of storage material provided at different locations in the memory structure, the first and second types of storage material having different characteristics.

### Claim 16 (depends on 15)

The memory structure of claim 15, wherein the first and second types of storage material comprise, respectively, first and second tunnel dielectric layers, the first tunnel dielectric layer being thicker than the second tunnel dielectric layer.

### Claim 17 (depends on 15)

The memory structure of claim 15, wherein the first tunnel dielectric layer has a thickness of 5 nm or more.

### Claim 18 (depends on 15)

The memory structure of claim 15, wherein the second tunnel dielectric layer has a thickness of 3 nm or less.

### Claim 19 (depends on 1)

The memory structure of claim 1, wherein the storage layer comprises an oxide-nitride-oxide material.

### Claim 20

A method for providing a memory structure, comprising:
providing a semiconductor substrate having a substantially planar surface;
providing a first stack of active strips and a second stack of active strips formed over the surface of the semiconductor substrate and separated by a predetermined distance along a first direction substantially parallel the planar surface, wherein each stack of active strips comprises two or more active strips provided one on top of another, with adjacent active strips being isolated from each other by a first dielectric layer, the active strips being substantially aligned lengthwise with each other along a second direction that is substantially also parallel to the planar surface but orthogonal the first direction, and wherein each active strip comprises a first semiconductor layer of a first conductivity type provided in one or more recessed portions of a second dielectric layer sandwiched between a second semiconductor layer and a third semiconductor layer each of a second conductivity type, the first, second and third semiconductor layers being stacked along a third direction that is substantially normal to the planar surface;
providing a storage layer; and
providing a plurality of conductors each extending lengthwise along a third direction that is substantially perpendicular to the planar surface, each conductor being within a group of the conductors that are provided between the first stack of active strips and the second stack of active strips and separated from each stack of active strips by the storage layer, thereby forming in each active strip at least one NOR string, each NOR string including a plurality of storage transistors that are formed out of the first, the second and the third semiconductor layers of the active strip and their adjacent storage layer and the conductors within the group.

### Claim 21 (depends on 20)

The method of claim 20, wherein each active strip further comprises providing at least one metallic layer that is in electrical contact with, and in substantial alignment lengthwise with, one of the second semiconductor layer and the third semiconductor layer.

### Claim 22 (depends on 20)

The method of claim 20, further comprising providing a metallic layer contacting one of the second and the third semiconductor layer.

### Claim 23 (depends on 22)

The memory structure of claim 22, further comprising:
providing a layer of non-conductive material that is located between the second semiconductor layer and the first dielectric layer; and
providing a metallic layer that occupies cavities or recesses formed in the non-conductive layer, the metallic being in electrical contact with the second semiconductor layer.

### Claim 24 (depends on 20)

The method of claim 20 wherein the non-conductive layer comprises one or more of: silicon oxide, boron doped silicon oxide, phosphorus doped silicon oxide, boron phosphorus doped silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon oxygen hydrogen, germanium, and any combinations thereof.

### Claim 25 (depends on 23)

The method of claim 23, wherein the non-conductive layer is porous.

### Claim 26 (depends on 22)

The method of claim 22, wherein the metallic layer further comprises two or more sublayers where a first sublayer is disposed adjacent to and in electrical contact with a second sublayer, and the first sublayer surrounds the second sublayer on three or more sides.

### Claim 27 (depends on 26)

The method of claim 26 wherein the thickness of the second sublayer is at least 1.5× the thickness of the first sublayer.

### Claim 28 (depends on 22)

The method of claim 22, wherein the metallic layer comprises one or more of: titanium, titanium nitride, tungsten nitride, tungsten, titanium tungsten, tantalum, tantalum nitride, cobalt, chrome, molybdenum, niobium, and any alloys thereof.

### Claim 29 (depends on 22)

The method of claim 22, wherein the metallic layer is deposited by atomic layer deposition.

### Claim 30 (depends on 20)

The method of claim 20, further comprising providing a hard mask layer that includes one or more struts formed between two adjacent stacks of active strips, wherein each strut comprises an insulating layer physically connecting the adjacent stacks of active strips.

### Claim 31 (depends on 30)

The method of claim 30, wherein the strut is in contact with and disposed to adjacent stacks of active strips at only a portion of the height of one of the stacks of active strips.

### Claim 32 (depends on 30)

The method of claim 30, wherein each struct connects adjacent stacks of active strips at the top of the stacks.

### Claim 33 (depends on 30)

The method of claim 30, wherein each strut is in contact with and disposed to adjacent stacks of active strips along substantially the entire height of the memory structure.

### Claim 34 (depends on 20)

The method of claim 20, wherein the storage layer in the memory structure comprises first and second types of storage material provided at different locations in the memory structure, the first and second types of storage material having different characteristics.

### Claim 35 (depends on 34)

The method of claim 34, wherein the first and second types of storage material comprise, respectively, first and second tunnel dielectric layers, the first tunnel dielectric layer being thicker than the second tunnel dielectric layer.

### Claim 36 (depends on 34)

The method of claim 34, wherein the first tunnel dielectric layer has a thickness of 5 nm or more.

### Claim 37 (depends on 34)

The method of claim 34, wherein the second tunnel dielectric layer has a thickness of 3 nm or less.

### Claim 38 (depends on 20)

The method of claim 20, wherein the storage layer comprises an oxide-nitride-oxide material.