# US 11,309,330 B2 · Semiconductor device and manufacturing method of the semiconductor device

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- Number: US 11,309,330 B2
- Document ID: US11309330B2
- Status: Granted
- Kind: B2
- Application number: 16/942,478
- Filed: 2020-07-29
- Published: 2021-08-26
- Granted: 2022-04-19
- Earliest claimed: 2020-02-20
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Ki Hong Lee; Hwal Pyo Kim; Seung Woo Han
- Web page: https://patentgrep.com/patent/US11309330B2

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 64/516: {the thicknesses being non-uniform}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes: a stack structure including insulating layers and conductive layers, which are alternately stacked; a channel structure penetrating the stack structure; data storage patterns respectively interposed between the conductive layers and the channel structure; blocking patterns respectively interposed between the conductive layers and the data storage patterns; insulating patterns respectively interposed between the insulating layers and the channel structure; and insulative liners interposed between the insulating layers and the insulating patterns, the insulative liners respectively surrounding the insulating patterns.

## Claims

### Claim 1

A semiconductor device comprising:
a stack structure including insulating layers and conductive layers, which are alternately stacked;
a channel structure penetrating the stack structure;
data storage patterns respectively interposed between the conductive layers and the channel structure;
blocking patterns respectively interposed between the conductive layers and the data storage patterns;
insulating patterns respectively interposed between the insulating layers and the channel structure, wherein the insulating patterns are spaced apart from each other in a direction in which the insulating layers and the conductive layers are stacked; and
insulative liners interposed between the insulating layers and the insulating patterns, the insulative liners respectively surrounding the insulating patterns.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein each of the insulative liners is expanded:
between the conductive layers and the insulating patterns;
between the blocking patterns and the insulating patterns; and
between the data storage patterns and the insulating patterns.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein each of the insulative liners includes an oxide layer and a charge trap material included in the oxide layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein concave portions are defined between the data storage patterns and the blocking patterns, wherein the concave portions are filled with the insulative liners.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising a tunnel insulating layer surrounding the channel structure, the tunnel insulating layer being in contact with the insulating patterns and the data storage patterns.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the tunnel insulating layer is in contact with the insulative liners.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein, for each of the data storage patterns, a thickness of an end portion is different from a thickness of a central portion.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein sidewalls of the insulating patterns protrude farther toward the channel structure than sidewalls of the conductive layers.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein sidewalls of the insulative liners protrude farther toward the channel structure than sidewalls of the conductive layers.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein sidewalls of the data storage patterns protrude farther toward the channel structure than sidewalls of the insulating patterns and the insulative liners.

### Claim 11

A semiconductor device comprising:
a stack structure including insulating layers and conductive layers, which are alternately stacked;
a channel structure penetrating the stack structure;
insulating patterns respectively interposed between the insulating layers and the channel structure, the insulating patterns protruding farther toward the channel structure than the conductive layers, wherein the insulating patterns are spaced apart from each other in a direction in which the insulating layers and the conductive layers are stacked;
data storage patterns respectively interposed between the conductive layers and the channel structure, the data storage patterns protruding farther toward the channel structure than the insulating patterns; and
blocking patterns respectively interposed between the conductive layers and the data storage patterns.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, further comprising insulative liners respectively interposed between the insulating layers and the insulating patterns, the insulative liners respectively surrounding the insulating patterns.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein each of the insulative liners is expanded:
between the conductive layers and the insulating patterns;
between the blocking patterns and the insulating patterns; and
between the data storage patterns and the insulating patterns.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, wherein each of the insulative liners includes an oxide layer and a charge trap material included in the oxide layer.

### Claim 15 (depends on 12)

The semiconductor device of claim 12, wherein concave portions are defined between the data storage patterns and the blocking patterns, wherein the concave portions are filled with the insulative liners.

### Claim 16 (depends on 11)

The semiconductor device of claim 11, further comprising a tunnel insulating layer surrounding the channel structure, the tunnel insulating layer being in contact with the insulating patterns and the data storage patterns.

### Claim 17 (depends on 11)

The semiconductor device of claim 11, wherein, for each of the data storage patterns, a thickness of an end portion is different from a thickness of a central portion.

### Claim 18

A semiconductor device comprising:
a stack structure including insulating layers and conductive layers, which are alternately stacked;
a channel structure penetrating the stack structure;
data storage patterns respectively interposed between the conductive layers and the channel structure, wherein each of the data storage patterns include a curved surface;
blocking patterns respectively interposed between the conductive layers and the data storage patterns;
insulating patterns respectively interposed between the insulating layers and the channel structure; and
insulative liners interposed between the insulating layers and the insulating patterns, the insulative liners respectively surrounding the insulating patterns.