# US 11,309,326 B2 · Vertical semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,326 B2 - Document ID: US11309326B2 - Status: Granted - Kind: B2 - Application number: 16/832,389 - Filed: 2020-03-27 - Published: 2020-07-16 - Granted: 2022-04-19 - Earliest claimed: 2016-12-14 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jo-young Park; Chang-seok Kang; Chang-sup Lee; Se-mee Jang - Web page: https://patentgrep.com/patent/US11309326B2 ## CPC - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/35: with a cell select transistor, e.g. NAND - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10W 20/056: {by filling conductive material into holes, grooves or trenches} - H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning} - H10W 20/42: Vias, e.g. via plugs - H10W 20/43: Layouts of interconnections - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern. ## Claims ### Claim 1 A vertical semiconductor device comprising: a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns, wherein the conductive layer patterns include a first conductive layer pattern near the substrate and second conductive layer patterns farther away from the substrate, and the first conductive layer pattern is configured to extend from one side wall of an adjacent interlayer insulating layer pattern, and includes a pad region having a raised pad portion protruding from a surface of the first conductive layer pattern; an upper interlayer insulating layer covering the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug penetrating the upper interlayer insulating layer to be in contact with the raised pad portion of the first conductive layer pattern, wherein the horizontal length of the second conductive layer patterns become shorter as the second conductive layer patterns get farther away from the substrate in the vertical direction, and one sidewall of each of the second conductive layer patterns has an inclined portion, and wherein a first end of the raised pad portion and a second end of the raised pad portion opposite the first end are rounded. ### Claim 2 (depends on 1) The vertical semiconductor device of claim 1, wherein the horizontal length of the first conductive layer pattern is longer than horizontal distances of the second conductive layer patterns. ### Claim 3 (depends on 1) The vertical semiconductor device of claim 1, wherein an imaginary line connected to the sidewalls of the second conductive layer patterns is inclined in the vertical direction. ### Claim 4 (depends on 1) The vertical semiconductor device of claim 1, wherein one end of each of the second conductive layer patterns is rounded. ### Claim 5 (depends on 4) The vertical semiconductor device of claim 4, wherein one upper end of the second conductive layer patterns and one lower end of each of the second conductive layer patterns in the vertical direction are rounded. ### Claim 6 (depends on 1) The vertical semiconductor device of claim 1, wherein the conductive layer patterns further comprises a third conductive layer pattern below the first conductive layer pattern. ### Claim 7 (depends on 1) The vertical semiconductor device of claim 1, wherein the second end of the raised pad portion extends farther in a horizontal direction in which the first conductive layer pattern extends than an adjacent interlayer insulating layer pattern, and the raised pad portion is configured to occupy, from a top-down view, a portion exposed by the second conductive layer patterns. ### Claim 8 (depends on 1) The vertical semiconductor device of claim 1, wherein the upper surface of the raised pad portion is positioned between a lower surface of an adjacent second conductive layer pattern and an upper surface of the first conductive layer pattern. ### Claim 9 (depends on 1) The vertical semiconductor device of claim 1, wherein some of the interlayer insulating layer patterns comprise a recessed portion recessed from one end of respective adjacent second conductive layer patterns. ### Claim 10 (depends on 9) The vertical semiconductor device of claim 9, wherein each recessed portion is filled with the upper interlayer insulating layer. ### Claim 11 (depends on 1) The vertical semiconductor device of claim 1, wherein the second end of the raised pad portion is separated from the first end of the raised pad portion in a horizontal direction in which the first conductive layer pattern extends. ### Claim 12 A vertical semiconductor device comprising: a vertical structure protruding in a vertical direction on a substrate of a cell block region and including a channel layer; a plurality of conductive layer patterns stacked while being spaced apart from each other by a plurality of interlayer insulating layer patterns in the vertical direction; and a contact plug in contact with a pad region which is at an edge of a first conductive layer pattern of the conductive layer patterns, the pad region including a raised pad portion protruding from a surface of the first conductive layer pattern, wherein second conductive layer patterns of the conductive layer patterns have an inclined form in which the horizontal distances from the vertical structure to an end of second conductive layer patterns become shorter as the second conductive layer patterns get farther away from the substrate in the vertical direction, and one end of each of the second conductive layer patterns is rounded, and wherein a first interlayer insulating layer pattern of the interlayer insulating patterns comprises a recessed portion recessed from one end of respective adjacent second conductive layer patterns. ### Claim 13 (depends on 12) The vertical semiconductor device of claim 12, wherein the conductive layer patterns are a word line, a string selection line, or a ground selection line. ### Claim 14 (depends on 12) The vertical semiconductor device of claim 12, wherein one end and an other end of the raised pad portion are rounded. ### Claim 15 (depends on 12) The vertical semiconductor device of claim 12, wherein the raised pad portion includes a first end and a second end opposite the first end, the second end of the raised pad portion is separated from the first end of the raised pad portion in a horizontal direction in which the first conductive layer pattern extends, and the first end of the raised pad portion is separated from an adjacent recessed portion in a horizontal direction in which the first conductive layer pattern extends. ### Claim 16 (depends on 12) The vertical semiconductor device of claim 12, wherein the upper surface of the raised pad portion is positioned between a lower surface of an adjacent second conductive layer pattern and an upper surface of the first conductive layer pattern. ### Claim 17 A vertical semiconductor device, comprising: a plurality of conductive layer patterns being stacked in a vertical structure on a substrate and being spaced apart from each other by a plurality of interlayer insulating layer patterns in the vertical direction; and a contact plug in contact with a pad region which is at an edge of a first conductive layer pattern of the conductive layer patterns, wherein the edge of the first conductive layer pattern includes a raised pad portion in the pad region and through which the contact plug passes, and the raised pad portion is rounded on opposite sides of the contact plug on the first conductive layer pattern, wherein second conductive layer patterns of the conductive layer patterns have an inclined form in which the horizontal distances become shorter as the second conductive layer patterns get farther away from the substrate in the vertical direction. ### Claim 18 (depends on 17) The vertical semiconductor device of claim 17, wherein some of interlayer insulating layer patterns comprise a recessed portion recessed from one end of an adjacent second conductive layer pattern, and one end of each of the second conductive layer patterns is rounded. ### Claim 19 (depends on 17) The vertical semiconductor device of claim 17, wherein the upper surface of the raised pad portion is positioned between a lower surface of an adjacent second conductive layer pattern and an upper surface of the first conductive layer pattern. ### Claim 20 (depends on 17) The vertical semiconductor device of claim 17, wherein one sidewall of each of the second conductive layer patterns has an inclined portion.