# US 11,309,324 B2 · Compact memory cell with a shared conductive word line and methods of making such a memory cell

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- Number: US 11,309,324 B2
- Document ID: US11309324B2
- Status: Granted
- Kind: B2
- Application number: 16/940,522
- Filed: 2020-07-28
- Published: 2022-02-03
- Granted: 2022-04-19
- Earliest claimed: 2020-07-28
- Assignees: Globalfoundries Singapore Pte. Ltd.
- Applicants: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Inventors: Yongshun Sun; Eng Huat Toh; Shyue Seng Tan; Kiok Boone Elgin Quek
- Web page: https://patentgrep.com/patent/US11309324B2

## CPC

- H10B 43/30: characterised by the memory core region
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- H10B 41/30: characterised by the memory core region
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling}
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/037: {comprising charge-trapping insulators}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An illustrative device disclosed herein includes a first memory cell comprising a first memory gate positioned above an upper surface of a semiconductor substrate and a second memory cell comprising a second memory gate positioned above the upper surface of the semiconductor substrate. In this example, the device also includes a conductive word line structure positioned above the upper surface of the semiconductor substrate between the first and second memory gates, wherein the conductive word line structure is shared by the first and second memory cells.

## Claims

### Claim 1

A device, comprising:
a semiconductor substrate having an upper surface;
a first memory cell comprising a first memory gate positioned above the upper surface of the semiconductor substrate and a first gate cap above the first memory gate;
a first sidewall spacer positioned adjacent the first memory gate;
a second memory cell comprising a second memory gate positioned above the upper surface of the semiconductor substrate and a second gate cap above the second memory gate;
a second sidewall spacer positioned adjacent the second memory gate;
a conductive word line structure positioned above the upper surface of the semiconductor substrate between the first and second memory gates, wherein the conductive word line structure is shared by the first and second memory cells, wherein an upper surface of the conductive word line structure is above an upper surface of the first gate cap and an upper surface of the second gate cap
a first conductive select gate structure for the first memory cell, the first conductive select gate structure being positioned above the upper surface of the semiconductor substrate adjacent the first sidewall spacer; and
a second conductive select gate structure for the second memory cell, the second conductive select gate structure being positioned above the upper surface of the semiconductor substrate adjacent the second sidewall spacer.

### Claim 2 (depends on 1)

The device of claim 1, wherein:
the first sidewall spacer positioned adjacent the first memory gate; and
the second sidewall spacer positioned adjacent the second memory gate, wherein the conductive word line structure physically contacts both the first and second sidewall spacers.

### Claim 3 (depends on 2)

The device of claim 2, further comprising:
a first conductive select gate structure for the first memory cell, the first conductive select gate structure being positioned above the upper surface of the semiconductor substrate adjacent the first memory gate, wherein the first conductive select gate structure physically contacts the first sidewall spacer; and
a second conductive select gate structure for the second memory cell, the second conductive select gate structure being positioned above the upper surface of the semiconductor substrate adjacent the second memory gate, wherein the second conductive select gate structure physically contacts the second sidewall spacer.

### Claim 4 (depends on 1)

The device of claim 1, further comprising:
a first conductive select gate structure for the first memory cell, the first conductive select gate structure being positioned above the upper surface of the semiconductor substrate adjacent the first memory gate; and
a second conductive select gate structure for the second memory cell, the second conductive select gate structure being positioned above the upper surface of the semiconductor substrate adjacent the second memory gate.

### Claim 5 (depends on 1)

The device of claim 1, further comprising:
a first doped region in the semiconductor substrate, wherein the first doped region functions as a source line for the first and second memory cells; and
a second doped region in the semiconductor substrate, wherein the second doped region functions as a bit line for the first and second memory cells.

### Claim 6 (depends on 1)

The device of claim 1, wherein each of the first and second memory gates comprise:
a gate insulation layer positioned above the semiconductor substrate;
a charge storage layer positioned above the gate insulation layer;
a blocking insulation layer positioned above the charge storage layer; and
a conductive gate electrode positioned above the blocking insulation layer.

### Claim 7 (depends on 1)

The device of claim 1, further comprising:
a first sidewall spacer positioned adjacent the first memory gate, wherein the first sidewall spacer physically contacts the first memory gate; and
a second sidewall spacer positioned adjacent the second memory gate, wherein the second sidewall spacer physically contacts the second memory gate.

### Claim 8

A device, comprising:
a semiconductor substrate having an upper surface;
a first memory cell comprising a first memory gate positioned above the upper surface of the semiconductor substrate and a first gate cap above the first memory gate;
a first sidewall spacer positioned adjacent the first memory gate;
a second memory cell comprising a second memory gate positioned above the upper surface of the semiconductor substrate and a second gate cap above the second memory gate;
a second sidewall spacer positioned adjacent the second memory gate;
a conductive word line structure positioned above the upper surface of the semiconductor substrate between the first and second sidewall spacers, wherein the conductive word line structure is shared by the first and second memory cells, and wherein an upper surface of the conductive word line structure is above an upper surface of the first gate cap and an upper surface of the second gate cap, and wherein the conductive word line structure covers a portion of the upper surfaces of the first gate cap and the second gate cap leaving a portion of the upper surfaces of the first gate cap and the second gate cap exposed;
a first conductive select gate structure for the first memory cell, the first conductive select gate structure being positioned above the upper surface of the semiconductor substrate adjacent the first sidewall spacer; and
a second conductive select gate structure for the second memory cell, the second conductive select gate structure being positioned above the upper surface of the semiconductor substrate adjacent the second sidewall spacer.

### Claim 9 (depends on 8)

The device of claim 8, wherein the conductive word line structure physically contacts both the first sidewall spacer and the second sidewall spacer, wherein the first conductive select gate structure physically contacts the first sidewall spacer and wherein the second conductive select gate structure physically contacts the second sidewall spacer.

### Claim 10 (depends on 8)

The device of claim 8, further comprising:
a first doped region in the semiconductor substrate, wherein the first doped region functions as a source line for the first and second memory cells; and
a second doped region in the semiconductor substrate, wherein the second doped region functions as a bit line for the first and second memory cells.

### Claim 11 (depends on 8)

The device of claim 8, wherein the first sidewall spacer physically contacts the first memory gate and wherein the second sidewall spacer physically contacts the second memory gate.