# US 11,309,322 B2 · Semiconductor memory device

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- Number: US 11,309,322 B2
- Document ID: US11309322B2
- Status: Granted
- Kind: B2
- Application number: 16/569,215
- Filed: 2019-09-12
- Published: 2020-09-24
- Granted: 2022-04-19
- Earliest claimed: 2019-03-18
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Ryota Fujitsuka; Kenta Yamada; Takanori Yamanaka; Takayuki Okada; Hirokazu Ishigaki; Hiroki Kishi; Nobushi Matsuura; Takashi Yamane; Ryota Suzuki
- Web page: https://patentgrep.com/patent/US11309322B2

## CPC

- H10B 43/00: EEPROM devices comprising charge-trapping gate insulators
- H10B 43/10: characterised by the top-view layout
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 30/694: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/697: {having trapping at multiple separated sites, e.g. multi-particles trapping sites}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 64/514: {characterised by the insulating layers}
- H10P 14/6682: {the compound being a silane, e.g. disilane, methylsilane or chlorosilane}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor memory device according to an embodiment includes a semiconductor substrate; a laminated body formed by laminating a plurality of electrode layers on the semiconductor substrate; a memory film provided in the laminated body and including a first block insulation film disposed in a direction perpendicular to the electrode layer, a charge storage film facing the first block insulation film, a tunnel insulation film facing the charge storage film, and a channel film facing the tunnel insulation film; and a barrier layer provided at at least one of interface between the plurality of electrode layers and the memory film and an interface in the memory film and mainly composed of carbon.

## Claims

### Claim 1

A semiconductor memory device comprising:
a semiconductor substrate;
a laminated body formed by laminating a plurality of electrode layers on the semiconductor substrate;
a memory film provided in the laminated body and including a first block insulation film disposed in a direction perpendicular to the electrode layers, a charge storage film facing the first block insulation film, a tunnel insulation film facing the charge storage film, and a channel film facing the tunnel insulation film; and
a barrier layer provided an interface in the memory film and mainly composed of carbon, wherein
the charge storage film includes a first silicon nitride layer facing the first block insulation film, a silicon oxynitride layer facing the first silicon nitride layer, and a second silicon nitride layer facing the silicon oxynitride layer, and
each of the plurality of electrode layers includes a metal layer, a barrier metal layer that covers the metal layer, and second block insulation film that covers the harrier metal layer, and a carbon concentration of the barrier layer is within the range of 0.1 to 10.0 atomic, and the barrier layer has a thickness equal to or less than 0.5 nanometers, and the barrier layer is provided at interface between the second silicon nitride layer and the tunnel insulation film.

### Claim 2 (depends on 1)

The semiconductor memory device according to claim 1, wherein
the barrier layer contains the carbon, silicon, and nitrogen.

### Claim 3 (depends on 2)

The semiconductor memory device according to claim 2, wherein the silicon content of the first silicon nitride layer is less than the silicon content of the second silicon nitride layer.

### Claim 4 (depends on 2)

The semiconductor memory device according to claim 2, wherein the silicon content of the first silicon nitride layer is greater than the silicon content of the second silicon nitride layer.