# US 11,309,320 B2 · Semiconductor storage device

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- Number: US 11,309,320 B2
- Document ID: US11309320B2
- Status: Granted
- Kind: B2
- Application number: 17/025,191
- Filed: 2020-09-18
- Published: 2021-01-07
- Granted: 2022-04-19
- Earliest claimed: 2018-04-02
- Assignees: Socionext Inc.
- Applicants: Socionext Inc.
- Inventors: Tomoyuki Yamada
- Web page: https://patentgrep.com/patent/US11309320B2

## CPC

- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10B 20/25: One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A nonvolatile memory cell using vertical nanowire (VNW) FETs includes a program element of which a gate is connected to a word line, and a switch element that is provided between the program element and a bit line and of which a gate is connected to the word line. The program element and the switch element are each constituted by one or a plurality of VNW FETs, and these VNW FETs are arranged in a line in a first direction.

## Claims

### Claim 1

A semiconductor memory device comprising a nonvolatile memory cell, wherein
the memory cell includes
a program element of which a gate is connected to a word line, and
a switch element that is provided between the program element and a bit line and of which a gate is connected to the word line,
the program element and the switch element are each constituted by one or a plurality of vertical nanowire (VNW) FETs, and
the VNW FETs constituting the program element and the switch element are arranged in a line in a first direction.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, wherein
the memory cell includes
a gate interconnect that extends in the first direction and is connected with gates of the VNW FETs constituting the program element and the switch element.

### Claim 3 (depends on 2)

The semiconductor memory device of claim 2, wherein
the word line extends in the first direction, and
the VNW FETs constituting the program element and the switch element, the gate interconnect, and the word line overlap one another as viewed from top.

### Claim 4 (depends on 1)

The semiconductor memory device of claim 1, wherein
the switch element includes a VNW FET of which a top electrode is connected with the bit line.

### Claim 5 (depends on 1)

The semiconductor memory device of claim 1, wherein
the switch element includes serially connected first, second, and third VNW FETs, and
top electrodes of the first and second VNW FETs are mutually connected and bottom electrodes of the second and third VNW FETs are mutually connected.

### Claim 6 (depends on 2)

The semiconductor memory device of claim 2, wherein
the gate interconnect has a first interconnect portion extending from a side of the program element opposite to the switch element in the first direction, and
the word line is connected to the first interconnect portion.

### Claim 7

A semiconductor memory device comprising a nonvolatile memory cell, wherein
the memory cell includes
a program element of which a gate is connected to a first word line, and
a switch element that is provided between the program element and a bit line and of which a gate is connected to a second word line,
the program element and the switch element are each constituted by one or a plurality of vertical nanowire (VNW) FETs, and
the VNW FETs constituting the program element and the switch element are arranged in a line in a first direction.

### Claim 8 (depends on 7)

The semiconductor memory device of claim 7, wherein
the bit line extends in the first direction, and
the VNW FETs constituting the program element and the switch element and the bit line overlap each other as viewed from top.

### Claim 9 (depends on 7)

The semiconductor memory device of claim 7, wherein
the switch element includes a VNW FET of which a top electrode is connected with the bit line.

### Claim 10 (depends on 7)

The semiconductor memory device of claim 7, wherein
the switch element includes serially connected first, second, and third VNW FETs, and
top electrodes of the first and second VNW FETs are mutually connected and bottom electrodes of the second and third VNW FETs are mutually connected.

### Claim 11 (depends on 7)

The semiconductor memory device of claim 7, wherein
the first and second word lines extend in a second direction perpendicular to the first direction.

### Claim 12 (depends on 11)

The semiconductor memory device of claim 11, wherein
the first and second word lines do not overlap the VNW FETs constituting the program element and the switch element as viewed from top.