# US 11,309,319 B2 · Structures and SRAM bit cells integrating complementary field-effect transistors

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- Number: US 11,309,319 B2
- Document ID: US11309319B2
- Status: Granted
- Kind: B2
- Application number: 16/984,468
- Filed: 2020-08-04
- Published: 2020-11-19
- Granted: 2022-04-19
- Earliest claimed: 2019-03-07
- Assignees: GlobalFoundries U.S. Inc.
- Applicants: GLOBALFOUNDRIES U.S. Inc.
- Inventors: Randy W. Mann; Bipul C. Paul; Julien Frougier; Ruilong Xie
- Web page: https://patentgrep.com/patent/US11309319B2

## CPC

- H10B 10/12: {comprising a MOSFET load element}
- H10B 10/125: {the MOSFET being a thin film transistor [TFT]}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/853: {comprising FinFETs}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0696: {by using sacrificial placeholders, e.g. using sacrificial plugs}
- H10W 20/0698: {Local interconnections}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Structures and static random access memory bit cells including complementary field effect transistors and methods of forming such structures and bit cells. A first complementary field-effect transistor has a first storage nanosheet transistor, a second storage nanosheet transistor stacked over the first storage nanosheet transistor, and a first gate electrode shared by the first storage nanosheet transistor and the second storage nanosheet transistor. A second complementary field-effect transistor has a third storage nanosheet transistor, a fourth storage nanosheet transistor stacked over the third storage nanosheet transistor, and a second gate electrode shared by the third storage nanosheet transistor and the fourth storage nanosheet transistor. The first gate electrode and the second gate electrode are arranged in a spaced arrangement along a longitudinal axis. All gate electrodes of the SRAM bitcell may be arranged in a 1CPP layout.

## Claims

### Claim 1

A static random access memory (SRAM) bit cell comprising:
a first inverter including a first complementary field-effect transistor, the first complementary field-effect transistor having a first shared gate electrode, a first source/drain region, and a second source/drain region arranged over the first source/drain region;
a second inverter that is cross-coupled with the first inverter, the second inverter including a second complementary field-effect transistor having a second shared gate electrode;
an isolation layer comprised of a first dielectric material;
a pillar comprised of a second dielectric material, the pillar extending in a vertical direction from the isolation layer;
a first pass-gate transistor coupled with the first inverter, the first pass-gate transistor having a third gate electrode and a third source/drain region; and
a second pass-gate transistor coupled with the second inverter, the second pass-gate transistor having a fourth gate electrode,
wherein the first shared gate electrode, the second shared gate electrode, the third gate electrode, and the fourth gate electrode are arranged in a 1CPP layout, and the first source/drain region and the second source/drain region are arranged over the isolation layer and adjacent to the pillar.

### Claim 2 (depends on 1)

The SRAM bit cell of claim 1 wherein the first pass-gate transistor and the second pass-gate transistor are nanosheet field-effect transistors.

### Claim 3 (depends on 1)

The SRAM bit cell of claim 1 further comprising:
a conductive spacer coupled with the first source/drain region and the second source/drain region.

### Claim 4 (depends on 3)

The SRAM bit cell of claim 3 further comprising:
a local interconnect arranged to couple the conductive spacer with the second shared gate electrode of the second complementary field-effect transistor.

### Claim 5 (depends on 3)

The SRAM bit cell of claim 3 wherein the first shared gate electrode, the second shared gate electrode, the third gate electrode, and the fourth gate electrode are arranged in a first spaced arrangement along a longitudinal axis.

### Claim 6 (depends on 5)

The SRAM bit cell of claim 5 wherein the conductive spacer is aligned substantially parallel to the longitudinal axis.

### Claim 7 (depends on 3)

The SRAM bit cell of claim 3 wherein the conductive spacer couples the first source/drain region and the second source/drain region with the third source/drain region.

### Claim 8 (depends on 1)

The SRAM bit cell of claim 1 wherein the first source/drain region and the second source/drain region are in direct contact with the pillar.

### Claim 9 (depends on 1)

The SRAM bit cell of claim 1 further comprising:
a conductive spacer coupled with the first source/drain region and the second source/drain region,
wherein the first source/drain region, the second source/drain region, and the conductive spacer are in direct contact with the pillar.

### Claim 10 (depends on 9)

The SRAM bit cell of claim 9 wherein the first shared gate electrode, the second shared gate electrode, the third gate electrode, and the fourth gate electrode are arranged in a first spaced arrangement along a longitudinal axis.

### Claim 11 (depends on 10)

The SRAM bit cell of claim 10 wherein the conductive spacer is aligned substantially parallel to the longitudinal axis.

### Claim 12 (depends on 9)

The SRAM bit cell of claim 9 further comprising:
a local interconnect arranged to couple the conductive spacer with the second shared gate electrode of the second complementary field-effect transistor.

### Claim 13 (depends on 1)

The SRAM bit cell of claim 1 wherein the first dielectric material is silicon dioxide, and the second dielectric material is silicon carbide.

### Claim 14

A method of forming a static random access memory (SRAM) bit cell, the method comprising:
forming a first inverter that includes a first complementary field-effect transistor, wherein a first source/drain region of the first complementary field-effect transistor is formed on an isolation layer comprised of a first dielectric material, and a second source/drain region of the first complementary field-effect transistor is formed over the first source/drain region;
etching an opening extending through the first source/drain region and the second source/drain region to the isolation layer;
depositing a second dielectric material in the opening to define a pillar;
forming a second inverter that is cross-coupled with the first inverter;
forming a first pass-gate transistor coupled with the first inverter; and
forming a second pass-gate transistor coupled with the second inverter,
wherein the first complementary field-effect transistor has a first shared gate electrode, the second inverter includes a second complementary field-effect transistor having a second shared gate electrode, the first pass-gate transistor has a third gate electrode, the second pass-gate transistor has a fourth gate electrode, and the first shared gate electrode, the second shared gate electrode, the third gate electrode, and the fourth gate electrode are arranged in a 1CPP layout.

### Claim 15 (depends on 14)

The method of claim 14 wherein the first pass-gate transistor and the second pass-gate transistor are nanosheet field-effect transistors.

### Claim 16 (depends on 14)

The method of claim 14 wherein the first pass-gate transistor includes a third source/drain region, and further comprising:
forming a conductive spacer coupled with the first source/drain region and the second source/drain region.

### Claim 17 (depends on 16)

The method of claim 16 further comprising:
forming a local interconnect arranged to couple the conductive spacer with the second shared gate electrode of the second complementary field-effect transistor.

### Claim 18 (depends on 14)

The method of claim 14 wherein the first source/drain region and the second source/drain region are in direct contact with the pillar.

### Claim 19 (depends on 14)

The method of claim 14 further comprising:
forming a conductive spacer coupled with the first source/drain region and the second source/drain region,
wherein the first source/drain region, the second source/drain region, and the conductive spacer are in direct contact with the pillar.

### Claim 20 (depends on 14)

The method of claim 14 wherein the first dielectric material is silicon dioxide, and the second dielectric material is silicon carbide.