# US 11,309,317 B2 · Semiconductor structure having a dummy gate with an interlayer dielectric layer therein

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- Number: US 11,309,317 B2
- Document ID: US11309317B2
- Status: Granted
- Kind: B2
- Application number: 16/722,180
- Filed: 2019-12-20
- Published: 2020-04-23
- Granted: 2022-04-19
- Earliest claimed: 2017-03-07
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Fei Zhou
- Web page: https://patentgrep.com/patent/US11309317B2

## CPC

- H10B 10/12: {comprising a MOSFET load element}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 95/04: {Planarisation of conductive or resistive materials}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/8316: {the IGFETs characterised by having gate sidewall spacers specially adapted for integration}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 86/011: {comprising FinFETs}
- H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor structure and fabrication method are provided. The method includes: providing a base substrate including a first region, a second region and a third region between the first and the second region; forming a dummy gate structure extending from the first region to the second region and through the third region; forming first doped source/drain regions in the base substrate on both sides of the dummy gate structure in the first region; forming second doped source/drain regions in the base substrate on both sides of the dummy gate structure in the second region; forming an opening in the dummy gate structure in the third region and exposing the base substrate in the third region; and forming an interlayer dielectric layer within the opening to have a top surface coplanar with the dummy gate structure.

## Claims

### Claim 1

A semiconductor structure comprising:
a base substrate including a first region, a second region and a third region between the first and second region;
a dummy gate structure extending across the first region and the second region and dummy gate sidewall spacers surrounding the dummy gate structure;
first doped source/drain regions in the base substrate on both sides of the dummy gate structure in the first region;
second doped source/drain regions in the base substrate on both sides of the dummy gate structure in the second region;
an interlayer dielectric layer in the dummy gate structure in the third region and on the base substrate in the third region, wherein the interlayer dielectric layer has a top surface higher than a top surface of the dummy gate structure;
a first sidewall spacer formed on the sidewalls of the interlayer dielectric layer; and
a second sidewall spacer on the first sidewall spacer.

### Claim 2 (depends on 1)

The semiconductor structure according to claim 1, wherein:
the first sidewall spacer is made of a material including silicon nitride, and has a thickness of about 2 urn to about 3 nm.

### Claim 3 (depends on 1)

The semiconductor structure according to claim 1, wherein:
the second sidewall spacer is made of a material including silicon oxide and has a thickness of about 10 angstroms to about 50 angstroms.

### Claim 4 (depends on 1)

The semiconductor structure according to claim 1, wherein:
the dummy gate structure share a same doped source/drain region with an adjacent dummy gate structure.