# US 11,309,316 B1 · Semiconductor device with single step height and method for fabricating the same

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- Number: US 11,309,316 B1
- Document ID: US11309316B1
- Status: Granted
- Kind: B1
- Application number: 17/074,873
- Filed: 2020-10-20
- Published: 2022-04-21
- Granted: 2022-04-19
- Earliest claimed: 2020-10-20
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Hui-Lin Chen; Mao-Ying Wang; Yu-Ting Lin; Lai-Cheng Tien
- Web page: https://patentgrep.com/patent/US11309316B1

## CPC

- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/485: {Bit line contacts}
- H10B 12/50: {Peripheral circuit region structures}
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The method for fabricating the semiconductor device includes providing a substrate including an array area and a peripheral area adjacent to the array area, forming word line structures and source/drain regions in the array area, and a word line protection layer on the array area, forming a first hard mask layer over the substrate and having a step height adjacent to a border between the array area and the peripheral area, forming a bit line contact in the array area and between the word line structures by using the first hard mask layer as a pattern guide, and forming a gate electrode layer on the peripheral area.

## Claims

### Claim 1

A method for fabricating a semiconductor device, comprising:
providing a substrate comprising an array area and a peripheral area adjacent to the array area;
forming word line structures and source/drain regions in the array area, and a word line protection layer on the array area; wherein the step of forming the word line structures comprises:
forming word line trenches in the array area;
conformally forming word line dielectric layers in the word line trenches;
forming word line electrodes on the word line dielectric layers and in the word line trenches;
forming a layer of capping material filled the word line trenches and covered the array area and the peripheral area; and
removing the layer of capping material covered the peripheral area to turn the layer of capping material into word line capping layers and the word line protection layer;
wherein the word line dielectric layers, the word line electrodes, the word line capping layers together form the word line structures;
forming a first hard mask layer over the substrate and having a step height adjacent to a border between the array area and the peripheral area;
forming a bit line contact in the array area and between the word line structures by using the first hard mask layer as a pattern guide; and
forming a gate electrode layer on the peripheral area.

### Claim 2 (depends on 1)

The method for fabricating the semiconductor device of claim 1, further comprising a step of forming isolation structures in the substrate before the step of forming the word line structures, the source/drain regions, and the word line protection layer.

### Claim 3 (depends on 1)

The method for fabricating the semiconductor device of claim 1, wherein the word line electrodes comprise bottom conductive layers and top conductive layers, the bottom conductive layers are formed on the word line dielectric layers and in the word line trenches, and the top conductive layers are formed on the bottom conductive layers.

### Claim 4 (depends on 3)

The method for fabricating the semiconductor device of claim 3, wherein the bottom conductive layers are formed of polycrystalline silicon, polycrystalline germanium, or polycrystalline silicon germanium.

### Claim 5 (depends on 4)

The method for fabricating the semiconductor device of claim 4, wherein the top conductive layers are formed of tungsten, aluminum, titanium, copper, titanium nitride, or a combination thereof.

### Claim 6 (depends on 5)

The method for fabricating the semiconductor device of claim 5, wherein the word line dielectric layers are formed of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, or zirconium oxide.

### Claim 7 (depends on 6)

The method for fabricating the semiconductor device of claim 6, wherein the step of forming the word line trenches in the array area comprises:
forming a word line hard mask layer covered the array area and the peripheral area;
forming a first mask layer having a pattern of the word line structures on the word line hard mask layer;
transferring the pattern of the word line structures onto the word line hard mask layer by forming word line openings in the word line hard mask layer; and
performing a trench etch process to form the word line trenches.

### Claim 8 (depends on 7)

The method for fabricating the semiconductor device of claim 7, wherein an etch rate ratio of the substrate to the word line hard mask layer is between about 100:1 and about 10:1 during the trench etch process.

### Claim 9 (depends on 8)

The method for fabricating the semiconductor device of claim 8, wherein the word line hard mask layer is formed of silicon nitride.

### Claim 10 (depends on 9)

The method for fabricating the semiconductor device of claim 9, wherein the bit line contact is formed of polycrystalline silicon, polycrystalline germanium, polycrystalline silicon germanium, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminides, or combinations thereof.

### Claim 11 (depends on 10)

The method for fabricating the semiconductor device of claim 10, wherein the step of forming the bit line contact comprises:
forming a bit line contact opening along the first hard mask layer and the word line protection layer and extending to the array area;
forming a layer of first conductive material filled the bit line contact opening; and
performing a planarization process until the word line hard mask layer is exposed to turn the layer of first conductive material into the bit line contact.

### Claim 12 (depends on 11)

The method for fabricating the semiconductor device of claim 11, wherein the word line capping layers are formed of silicon oxide, silicon oxynitride, silicon nitride oxide, or a high-k material.

### Claim 13 (depends on 12)

The method for fabricating the semiconductor device of claim 12, wherein the first hard mask layer is formed of a carbon film.

### Claim 14 (depends on 13)

The method for fabricating the semiconductor device of claim 13, wherein a substrate temperature of forming the first hard mask layer is between about 100° C. and about 700° C.

### Claim 15 (depends on 14)

The method for fabricating the semiconductor device of claim 14, wherein a pressure of forming the first hard mask layer is between 1 Torr and about 20 Torr.

### Claim 16 (depends on 15)

The method for fabricating the semiconductor device of claim 15, wherein the step of forming the gate electrode layer on the peripheral area comprises:
forming a layer of second conductive material over the array area and the peripheral area;
forming a layer of insulating material on the layer of second conductive material;
forming a mask layer above the peripheral area and covered a portion of the layer of insulating material;
performing an array etch process to turn the layer of second conductive material into the gate electrode layer on the peripheral area and turn the layer of insulating material into a peripheral protection layer on the gate electrode layer; and
removing the peripheral protection layer.

### Claim 17 (depends on 16)

The method for fabricating the semiconductor device of claim 16, wherein the gate electrode layer is formed of polycrystalline silicon, polycrystalline germanium, or polycrystalline silicon germanium.

### Claim 18 (depends on 17)

The method for fabricating the semiconductor device of claim 17, wherein the peripheral protection layer is formed of silicon oxide, silicon nitride, or silicon nitride oxide.