# US 11,309,313 B2 · Semiconductor device with landing pad of conductive polymer and method for fabricating the same

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- Number: US 11,309,313 B2
- Document ID: US11309313B2
- Status: Granted
- Kind: B2
- Application number: 16/992,986
- Filed: 2020-08-13
- Published: 2022-02-17
- Granted: 2022-04-19
- Earliest claimed: 2020-08-13
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Chia-Hsiang Hsu
- Web page: https://patentgrep.com/patent/US11309313B2

## CPC

- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10B 12/488: {Word lines}
- H10D 1/68: Capacitors having no potential barriers
- H10K 85/1135: {Polyethylene dioxythiophene [PEDOT]; Derivatives thereof}
- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/051: {by ion implantation}
- H10W 20/0523: {by irradiating with ultraviolet or particle radiation}
- H10W 20/082: {the openings being tapered via holes}
- H10W 20/432: {comprising crossing interconnections}
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 20/4473: {Conductive organic materials, e.g. conductive adhesives or conductive inks}
- H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present application discloses a semiconductor device with a landing pad of conductive polymer and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a dielectric layer disposed over the substrate, a plug disposed in the dielectric layer, and a landing pad of conductive polymer disposed over the dielectric layer. The method includes: providing a substrate; forming a dielectric layer with a plug over the substrate; performing an etching process to remove a portion of the dielectric layer to expose a protruding portion of the plug; forming a conductive polymer layer covering the dielectric layer and the protruding portion; and performing a thermal process to form a landing pad over the dielectric layer in a self-aligned manner. The landing pad of conductive polymer comprises a protruding portion of the plug, a first silicide layer disposed over the protruding portion, and a second silicide layer disposed on a sidewall of the protruding portion.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a dielectric layer disposed over the substrate;
a plug disposed in the dielectric layer, wherein the plug has a protruding portion with a first width; and
a landing pad disposed over the dielectric layer, wherein the landing pad comprises conductive polymer, and the landing pad has a second width greater than the first width of the protruding portion.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the landing further comprises a barrier layer between the protruding portion and the dielectric layer.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the conductive polymer layer comprises graphene.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the conductive polymer layer comprises conjugated polymer.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the conjugated polymer comprises polyethylenediox ythiophene (PEDOT) or polyaniline (PANI).

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising a capacitor contact positioned over the substrate, the landing pad is disposed over the capacitor contact, the capacitor contact having a neck portion and a head portion over the neck portion, wherein an upper width of the head portion is larger than an upper width of the neck portion, and the second width of the landing pad is greater than the upper width of the head portion.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the upper width of the head portion is larger than a bottom width of the head portion.

### Claim 8 (depends on 6)

The semiconductor device of claim 6, wherein the upper width of the neck portion is substantially the same as a bottom width of the head portion.

### Claim 9 (depends on 6)

The semiconductor device of claim 6, wherein the head portion has a curved sidewall.

### Claim 10 (depends on 6)

The semiconductor device of claim 6, wherein the head portion has tapered profile.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, further comprising:
a bit line contact disposed over the substrate and a bit line disposed over the bit line contact, wherein the bit line is an undulating stripe extending between two adjacent capacitor contacts positioned over the substrate; and
a capacitor structure disposed over the landing pad.

### Claim 12

A method for fabricating a semiconductor device, comprising:
providing a substrate;
forming a dielectric layer with a plug over the substrate;
performing an etching process to remove a portion of the dielectric layer to expose a protruding portion of the plug;
forming a conductive polymer layer covering the dielectric layer and the protruding portion, wherein the protruding portion has a first width; and
removing a portion of the conductive polymer layer to form a landing pad over the dielectric layer, wherein the landing pad has a second width greater than the first width of the protruding portion.

### Claim 13 (depends on 12)

The method for fabricating a semiconductor device of claim 12, further comprising: forming a barrier layer between the plug and the dielectric layer, and the etching process remove a portion of the dielectric layer to expose the protruding portion of the plug and a top portion of the barrier layer.

### Claim 14 (depends on 12)

The method for fabricating a semiconductor device of claim 12, wherein removing a portion of the conductive polymer layer comprises:
aligning a mask having a patterned hole above the conductive polymer layer; and
radiating charged particle beams through the patterned hole of the mask to form a patterned conductive polymer.

### Claim 15 (depends on 14)

The method for fabricating a semiconductor device of claim 14, wherein the conductive polymer layer is formed of a conjugated polymer.

### Claim 16 (depends on 14)

The method for fabricating a semiconductor device of claim 14, wherein a radiated area of the conductive polymer layer forms an insulating polymer layer, and the charged particle beams are one of electrons and ions.

### Claim 17 (depends on 14)

The method for fabricating a semiconductor device of claim 14, wherein the mask is a shadow mask, and the ions are ions of a material selected from the group consisting of H, Li, Na, K, Rb, Fr, F, Cl, Br, I, At, Ne, Kr, Xe, Rn, He, Ar, N, O, and Cs.

### Claim 18 (depends on 12)

The method for fabricating a semiconductor device of claim 12, further comprising:
forming a capacitor contact over the substrate, and the landing pad is formed over the capacitor contact;
wherein the capacitor contact has a neck portion and a head portion over the neck portion, and an upper width of the head portion is larger than an upper width of the neck portion.

### Claim 19 (depends on 18)

The method for fabricating the semiconductor device of claim 18, wherein forming a capacitor contact comprises:
forming a contact hole in a dielectric stack having a first layer and a second layer over the first layer;
removing a portion of the second layer around the contact hole to form a transformed hole having a narrow portion in the first layer and a wide portion in the second layer; and
filling a conductive material into the transformed hole.

### Claim 20 (depends on 19)

The method for fabricating the semiconductor device of claim 19, wherein the contact hole is formed integrally with a bit line trench in the second layer, and the method further comprises:
filling the bit line trench and a lower portion of the contact hole with a filling material;
wherein removing a portion of the second layer around the contact hole is performed after filling the lower portion of the contact hole with a sacrificial material.