# US 11,309,310 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,310 B2 - Document ID: US11309310B2 - Status: Granted - Kind: B2 - Application number: 16/827,187 - Filed: 2020-03-23 - Published: 2020-07-16 - Granted: 2022-04-19 - Earliest claimed: 2017-01-26 - Assignees: Rohm Co., Ltd. - Applicants: Rohm Co., Ltd. - Inventors: Kohei Shinsho - Web page: https://patentgrep.com/patent/US11309310B2 ## CPC - H10D 84/617: {Combinations of vertical BJTs and only diodes} - H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) - H10D 12/441: {Vertical IGBTs} - H10D 12/461: {having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions} - H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs} - H10D 62/104: {having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats} - H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions} - H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)} - H10D 62/108: {having localised breakdown regions, e.g. built-in avalanching regions (in self-protected thyristors H10D18/211)} - H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers} - H10D 62/142: {Anode regions of thyristors or collector regions of gated bipolar-mode devices} - H10D 64/112: {comprising multiple field plate segments} - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device includes a semiconductor layer of a first conductivity type having a first principal surface on one side and a second principal surface on the other side, the semiconductor layer in which a device formation region and an outer region outside the device formation region are set, a channel region of a second conductivity type formed in a surface layer portion of the first principal surface of the semiconductor layer in the device formation region, an emitter region of a first conductivity type formed in a surface layer portion of the channel region, a gate electrode formed at the first principal surface of the semiconductor layer in the device formation region, the gate electrode facing the channel region across a gate insulating film, a collector region of a second conductivity type formed in a surface layer portion of the second principal surface of the semiconductor layer in the device formation region, an inner cathode region of a first conductivity type formed in the surface layer portion of the second principal surface of the semiconductor layer in the device formation region, and an outer cathode region of a first conductivity type formed in the surface layer portion of the second principal surface of the semiconductor layer in the outer region. ## Claims ### Claim 1 A semiconductor device comprising: a semiconductor layer of a first conductivity type having a first principal surface on one side and a second principal surface on the other side, the semiconductor layer having a device formation region and an outer region outside the device formation region; a channel region of a second conductivity type formed in a surface layer portion of the first principal surface of the semiconductor layer in the device formation region; an emitter region of the first conductivity type formed in a surface layer portion of the channel region; an embedded gate electrode formed at the first principal surface of the semiconductor layer in the device formation region, the gate electrode facing the channel region across a gate insulating film; a drift region of the first conductivity type formed in the outer region; a collector region of the second conductivity type formed in a surface layer portion of the second principal surface of the semiconductor layer in the device formation region; an inner cathode region of the first conductivity type formed in the surface layer portion of the second principal surface of the semiconductor layer in the device formation region; an outer cathode region of the first conductivity type formed in the surface layer portion of the second principal surface of the semiconductor layer in the outer region; a gate pad formed on the first principal surface of the semiconductor layer, wherein the gate pad overlaps with a portion of the device formation region and a portion of the outer region, the gate pad extends from the outer region to the device formation region, and the gate pad is electrically connected to the embedded gate electrode; an IGBT (Insulated Gate Bipolar Transistor) channel structure formed by the embedded gate electrode, the first conductivity type emitter region, the second conductivity type channel region and the first conductivity type drift region; an inner diode formed in the device formation region, wherein the inner diode includes a cathode region of the first conductivity type as a cathode and the channel region of the second conductivity type as an anode; and a dummy channel structure formed in the device formation region and the outer region, wherein the inner cathode region of the first conductivity type includes dot-shaped pattern portions formed in a circular shape in the plan view, wherein the dot-shaped pattern portions are arranged in a matrix shape array to be spaced from each other in the cathode formation region, wherein the dummy channel structure has a structure similar to the IGBT channel structure except the point in which the first conductivity type emitter region is not included, and wherein the first conductivity type outer cathode region is not formed in a region immediately below the dummy channel structure. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, further comprising: an emitter electrode connected to the emitter region on the first principal surface of the semiconductor layer; and a collector electrode connected to the collector region, the inner cathode region, and the outer cathode region on the second principal surface of the semiconductor layer. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, further comprising: a terminal region of the second conductivity type formed in the surface layer portion of the first principal surface of the semiconductor layer along the channel region in the outer region. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, further comprising: an inner diode having the channel region serving as an anode and the inner cathode region serving as a cathode; and an outer diode having the terminal region serving as the anode and the outer cathode region serving as the cathode. ### Claim 5 (depends on 3) The semiconductor device according to claim 3, wherein the outer cathode region faces the terminal region across a region of the semiconductor layer. ### Claim 6 (depends on 3) The semiconductor device according to claim 3, wherein a bottom portion of the terminal region is positioned in the second principal surface side of the semiconductor layer with respect to a bottom portion of the channel region. ### Claim 7 (depends on 3) The semiconductor device according to claim 3, wherein the terminal region has a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the channel region. ### Claim 8 (depends on 3) The semiconductor device according to claim 3, wherein the outer region surrounds the device formation region in a plan view as viewed from a normal direction of the first principal surface of the semiconductor layer, and the terminal region surrounds the channel region in the plan view as viewed from the normal direction of the first principal surface of the semiconductor layer. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein the collector region is also formed in the surface layer portion of the second principal surface of the semiconductor layer in the outer region, and the outer cathode region passes through the collector region. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein the outer cathode region includes a pattern extending along a periphery of the device formation region. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein the outer cathode region includes a pattern whose portions are spaced from each other along a periphery of the device formation region. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, wherein the outer cathode region includes a first pattern extending along a periphery of the device formation region, and a second pattern whose portions are spaced from each other along the periphery of the device formation region. ### Claim 13 (depends on 1) The semiconductor device according to claim 1, wherein the inner cathode region passes through the collector region. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, wherein the inner cathode region includes a pattern whose portions are spaced from each other. ### Claim 15 (depends on 1) The semiconductor device according to claim 1, wherein the outer cathode region has a depth equal to a depth of the inner cathode region. ### Claim 16 (depends on 1) The semiconductor device according to claim 1, wherein the outer cathode region first conductivity type impurity concentration is equal to the inner cathode region first conductivity type impurity concentration. ### Claim 17 (depends on 1) The semiconductor device according to claim 1, wherein when a forward voltage of 1.6 V is applied between the emitter region and the collector region in a state where a voltage of 15 V is applied between the emitter region and the gate electrode, a forward current flowing between the emitter region and the collector region is not less than 2 A. ### Claim 18 (depends on 1) The semiconductor device according to claim 1, wherein when a forward voltage of 2 V is applied between the emitter region and the collector region in a state where a voltage of 15 V is applied between the emitter region and the gate electrode, a forward current flowing between the emitter region and the collector region is not less than 8 A. ### Claim 19 A semiconductor device comprising: a semiconductor layer of a first conductivity type having a first principal surface on one side and a second principal surface on the other side, the semiconductor layer having a device formation region and an outer region outside the device formation region; a channel region of a second conductivity type formed in a surface layer portion of the first principal surface of the semiconductor layer in the device formation region; an emitter region of the first conductivity type formed in a surface layer portion of the channel region; an embedded gate electrode formed at the first principal surface of the semiconductor layer in the device formation region, the gate electrode facing the channel region across a gate insulating film; a drift region of the first conductivity type formed in the outer region; a collector region of the second conductivity type formed in a surface layer portion of the second principal surface of the semiconductor layer in the device formation region; an inner cathode region of the first conductivity type formed in the surface layer portion of the second principal surface of the semiconductor layer in the device formation region; an outer cathode region of the first conductivity type formed in the surface layer portion of the second principal surface of the semiconductor layer in the outer region; a gate pad formed on the first principal surface of the semiconductor layer; an IGBT (Insulated Gate Bipolar Transistor) channel structure formed by the embedded gate electrode, the first conductivity type emitter region, the second conductivity type channel region and the first conductivity type drift region; and a dummy channel structure formed in the device formation region and the outer region, wherein the inner cathode region of the first conductivity type includes dot-shaped pattern portions formed in a circular shape in the plan view, wherein the outer cathode region of the first conductivity type includes dot-shaped pattern portions formed in a circular shape in the plan view, wherein the dummy channel structure has a structure similar to the IGBT channel structure except the point in which the first conductivity type emitter region is not included, and wherein the first conductivity type outer cathode region is not formed in a region immediately below the dummy channel structure.