# US 11,309,307 B2 · Integrated circuit filler and method thereof

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- Number: US 11,309,307 B2
- Document ID: US11309307B2
- Status: Granted
- Kind: B2
- Application number: 16/946,160
- Filed: 2020-06-08
- Published: 2020-09-24
- Granted: 2022-04-19
- Earliest claimed: 2016-06-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Tseng Chin Lo; Molly Chang; Ya-Wen Tseng; Chih-Ting Sun; Zi-Kuan Li; Bo-Sen Chang; Geng-He Lin
- Web page: https://patentgrep.com/patent/US11309307B2

## CPC

- H10D 89/10: Integrated device layouts
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- H10B 10/00: Static random access memory [SRAM] devices
- H10D 84/0126: {the components including insulated gates, e.g. IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- H10P 74/27: {Structural arrangements therefor}
- H10P 76/2041: {Photolithographic processes}
- H10P 74/20: characterised by the properties tested or measured, e.g. structural or electrical properties
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.

## Claims

### Claim 1

A method of semiconductor device fabrication, comprising:
identifying a first failure mode in a first portion of a circuit layout and selecting a first pre-designed filler cell having a first pattern corresponding to the first failure mode;
inserting a first standard filler cell and the first pre-designed filler cell in a gap adjacent to the first portion of the circuit layout; and
inspecting a patterned semiconductor layer using an electron beam (e-beam) inspection process, the patterned semiconductor layer including the first pattern.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
identifying a second failure mode in a second portion of the circuit layout and selecting a second pre-designed filler cell having a second pattern corresponding to the second failure mode; and
inserting the second pre-designed filler cell in the gap and adjacent to the second portion of the circuit layout.

### Claim 3 (depends on 2)

The method of claim 2, wherein the gap is disposed between the first portion of the circuit layout and the second portion of the circuit layout.

### Claim 4 (depends on 2)

The method of claim 2, wherein the first failure mode and the second failure mode are the same.

### Claim 5 (depends on 2)

The method of claim 2, wherein the first failure mode and the second failure mode are different.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
as part of a physical design flow, inserting the first pre-designed filler cell after a floorplanning step and as part of a placement step.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
prior to inserting the first pre-designed filler cell, removing a second standard filler cell from the gap; and
inserting the first pre-designed filler cell in the gap.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first pattern of the first pre-designed filler cell includes a repeated pattern array.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
prior to inspecting the patterned semiconductor layer, patterning the semiconductor layer such that the first pattern is transferred to the semiconductor layer to provide the patterned semiconductor layer.

### Claim 10 (depends on 1)

The method of claim 1, wherein the inspecting the patterned semiconductor layer includes inspecting patterns corresponding to both of the first standard filler cell and the first pre-designed filler cell using the e-beam inspection process, and wherein a first analysis cycle time for inspection of the first pre-designed filler cell is less than a second analysis cycle time for inspection of the first standard filler cell.

### Claim 11

A method of semiconductor device fabrication, comprising:
replacing a standard filler cell disposed within a gap with a redesigned filler cell, the gap adjacent to a functional cell, wherein the redesigned filler cell is selected based on a particular failure mode identified within the functional cell;
transferring a pattern of the redesigned filler cell to a substrate layer; and
inspecting the substrate layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein the standard filler cell includes an irregular pattern, and wherein the redesigned filler cell includes a repeated array.

### Claim 13 (depends on 11)

The method of claim 11, further comprising:
identifying a failure mode in the functional cell;
selecting the redesigned filler cell having a layout pattern associated with the identified failure mode; and
replacing the standard filler cell with the selected redesigned filler cell.

### Claim 14 (depends on 13)

The method of claim 13, wherein the functional cell is adjacent to the selected redesigned filler cell.

### Claim 15 (depends on 11)

The method of claim 11, wherein the replacing the standard filler cell with the redesigned filler cell is performed as part of at least one of a floorplanning step and a placement step of a physical design flow.

### Claim 16 (depends on 11)

The method of claim 11, further comprising:
patterning the substrate layer, wherein the patterning the substrate layer includes:
fabricating a mask including a layout pattern of the redesigned filler cell;
transferring, by way of a photolithography process, the layout pattern from the mask to the substrate layer.

### Claim 17 (depends on 11)

The method of claim 11, wherein the inspecting the substrate layer includes inspecting the substrate layer using an electron beam (e-beam) inspection process.

### Claim 18

A method, comprising:
inserting a pre-designed filler cell within a portion of a circuit layout, wherein a functional cell abuts a first side of the pre-designed filler cell and a first standard filler cell abuts a second side of the pre-designed filler cell, and wherein the inserting the pre-designed filler cell includes one of inserting the pre-designed filler cell in a gap within the portion of the circuit layout and replacing a second standard filler cell within the portion of the circuit layout;
patterning a semiconductor substrate to include a layout design of the pre-designed filler cell; and
performing an electron-beam inspection of the patterned semiconductor substrate.

### Claim 19 (depends on 18)

The method of claim 18, wherein the performing the electron-beam inspection further includes inspecting both of the first standard filler cell and the pre-designed filler cell, wherein a first analysis cycle time for inspection of the pre-designed filler cell is less than a second analysis cycle time for inspection of the first standard filler cell.

### Claim 20 (depends on 18)

The method of claim 18, wherein the layout design of the pre-designed filler cell includes a pattern associated with a particular failure mode, and wherein the functional cell is identified as including the particular failure mode.