# US 11,309,306 B2 · Stack-gate circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,306 B2 - Document ID: US11309306B2 - Status: Granted - Kind: B2 - Application number: 16/573,664 - Filed: 2019-09-17 - Published: 2020-04-02 - Granted: 2022-04-19 - Earliest claimed: 2018-09-28 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Yu-Tao Yang; Wen-Shen Chou; Yung-Chow Peng - Web page: https://patentgrep.com/patent/US11309306B2 ## CPC - H10D 89/10: Integrated device layouts - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06F 30/394: Routing (G06F30/396 takes precedence) - H10D 84/83: of only insulated-gate FETs [IGFET] - H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An integrated circuit includes an active zone having a center portion adjoining a first side portion and a second side portion. A first transistor having a gate formed over one of the first channel regions in the center portion has a first threshold-voltage. A second transistor having a gate formed over one of the second channel regions in the center portion has a second threshold-voltage. A third transistor having a gate formed over one of the third channel regions in the first side portion has a third threshold-voltage. A fourth transistor having a gate formed over one of the fourth channel regions in the second side portion has a fourth threshold-voltage. A first average of the first threshold-voltage and the second threshold-voltage is larger than a second average of the third threshold-voltage and the fourth threshold-voltage by a predetermined threshold-voltage offset. ## Claims ### Claim 1 An integrated circuit comprising: a first high-threshold transistor having a gate over a channel region in a high-threshold portion of an active zone, and a first low-threshold transistor having a gate over a channel region in a low-threshold portion of the active zone, wherein the gate of the first high-threshold transistor and the gate of the first low-threshold transistor are conductively connected together and configured to operate each of the first high-threshold transistor and the first low-threshold transistor in a corresponding saturation region, and wherein a drain of the first high-threshold transistor is conductively connected to a source of the first low-threshold transistor; and wherein a threshold-voltage of the first high-threshold transistor is larger than a threshold-voltage of the first low-threshold transistor. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the first high-threshold transistor and the first low-threshold transistor are p-type transistors. ### Claim 3 (depends on 1) The integrated circuit of claim 1, wherein the first high-threshold transistor and the first low-threshold transistor are n-type transistors. ### Claim 4 (depends on 1) The integrated circuit of claim 1, further comprising a second high-threshold transistor having a gate over a channel region in the high-threshold portion of the active zone, and a second low-threshold transistor having a gate over a channel region in the low-threshold portion of the active zone, wherein the gate of the second high-threshold transistor and the gate of the second low-threshold transistor are conductively connected together and configured to operate each of the second high-threshold transistor and the second low-threshold transistor in a corresponding saturation region, and wherein a drain of the second high-threshold transistor is conductively connected to a source of the second low-threshold transistor; wherein a threshold-voltage of the second high-threshold transistor is larger than a threshold-voltage of the second low-threshold transistor; and wherein the gate of the first low-threshold transistor and the gate of the second low-threshold transistor are conductively connected to a drain of the first low-threshold transistor. ### Claim 5 (depends on 1) The integrated circuit of claim 1, wherein a source of the first high-threshold transistor is conductively connected to a first conductive segment configured to maintain a first supply voltage, and a drain of the first low-threshold transistor is conductively connected to a second conductive segment configured to maintain a second supply voltage that is different from the first supply voltage. ### Claim 6 An integrated circuit comprising: an active zone, extending in a first direction, including a center portion adjoining a first side portion and a second side portion; a plurality of conductive segments extending in a second direction that is perpendicular to the first direction; a plurality of gate-strips extending in the second direction and conductively connected together, wherein the plurality of gate-strips includes, a first group of gate-strips intersecting the active zone over first channel regions in the center portion, a second group of gate-strips intersecting the active zone over second channel regions in the center portion, a third group of gate-strips intersecting the active zone over third channel regions in the first side portion, and a fourth group of gate-strips intersecting the active zone over fourth channel regions in the second side portion; wherein a first transistor having a gate formed over one of the first channel regions has a first threshold-voltage, a second transistor having a gate formed over one of the second channel regions has a second threshold-voltage, a third transistor having a gate formed over one of the third channel regions has a third threshold-voltage, and a fourth transistor having a gate formed over one of the fourth channel regions has a fourth threshold-voltage; and wherein a first difference between the first threshold-voltage and the second threshold-voltage is less than 10% of a first average of the first threshold-voltage and the second threshold-voltage, a second difference between the third threshold-voltage and the fourth threshold-voltage is less than 10% of a second average of the third threshold-voltage and the fourth threshold-voltage, and the first average is larger than the second average by a predetermined threshold-voltage offset. ### Claim 7 (depends on 6) The integrated circuit of claim 6, further comprising: a routing line, extending in the first direction, conductively connecting to each gate-strip in the plurality of gate-strips through a type-one via. ### Claim 8 (depends on 6) The integrated circuit of claim 6, further comprising: a first conductive segment extending in the second direction and intersecting with the active zone at a first intersection between the first channel regions and the second channel regions; a second conductive segment extending in the second direction and intersecting with the active zone at a second intersection, wherein both the first channel regions and the third channel regions are between the second intersection and the first intersection in the active zone; and a routing line, extending in the first direction, conductively connecting to each gate-strip in the plurality of gate-strips through a type-one via and conductively connecting to the second conductive segment through a type-two via. ### Claim 9 (depends on 7) The integrated circuit of claim 7, further comprising: a third conductive segment extending in the second direction and intersecting with the active zone at a third intersection, wherein both the second channel regions and the fourth channel regions are between the third intersection and the first intersection in the active zone. ### Claim 10 (depends on 6) The integrated circuit of claim 6, further comprising: a first pair of dummy gate-strips extending in the second direction and located between the first group of gate-strips and the third group of gate-strips, the dummy gate-strips in the first pair being separated by a first boundary between the first side portion of the active zone and the center portion of the active zone; and a second pair of dummy gate-strips extending in the second direction and located between the second group of gate-strips and the fourth group of gate-strips, the dummy gate-strips in the second pair being separated by a second boundary between the second side portion of the active zone and the center portion of the active zone. ### Claim 11 (depends on 6) The integrated circuit of claim 6, further comprising: a first routing line, extending in the first direction, conductively connecting to both a first active region in the center portion and a second active region in the first side portion, wherein both the first active region and the second active region are located between first channel regions and the third channel regions; and a second routing line, extending in the first direction, conductively connecting to both a third active region in the center portion and a fourth active region in the second side portion, wherein both the third active region and the fourth active region are located between second channel regions and the fourth channel regions. ### Claim 12 (depends on 6) The integrated circuit of claim 6, wherein the first difference between the first threshold-voltage and the second threshold-voltage is less than 5% of the first average of the first threshold-voltage and the second threshold-voltage. ### Claim 13 (depends on 6) The integrated circuit of claim 6, wherein the second difference between the third threshold-voltage and the fourth threshold-voltage is less than 5% of the second average of the third threshold-voltage and the fourth threshold-voltage. ### Claim 14 (depends on 6) The integrated circuit of claim 6, wherein the predetermined threshold-voltage offset is larger than 0.5 Volts. ### Claim 15 (depends on 6) The integrated circuit of claim 6, wherein the predetermined threshold-voltage offset is larger than 1.0 Volts. ### Claim 16 (depends on 6) The integrated circuit of claim 6, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are p-type transistors. ### Claim 17 (depends on 6) The integrated circuit of claim 6, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are n-type transistors. ### Claim 18 An integrated circuit comprising: an active zone, extending in a first direction, including a center portion adjoining a first side portion and a second side portion; a plurality of conductive segments extending in a second direction that is perpendicular to the first direction; a plurality of gate-strips extending in the second direction and conductively connected together, wherein the plurality of gate-strips includes, a first group of gate-strips intersecting the active zone over first channel regions in the center portion, a second group of gate-strips intersecting the active zone over second channel regions in the center portion, a third group of gate-strips intersecting the active zone over third channel regions in the first side portion, and a fourth group of gate-strips intersecting the active zone over fourth channel regions in the second side portion; wherein a first transistor having a gate formed over one of the first channel regions has a first threshold-voltage, a second transistor having a gate formed over one of the second channel regions has a second threshold-voltage, a third transistor having a gate formed over one of the third channel regions has a third threshold-voltage, and a fourth transistor having a gate formed over one of the fourth channel regions has a fourth threshold-voltage; a routing line, extending in the first direction, conductively connecting to each gate-strip in the plurality of gate-strips through a type-one via; and wherein each of the first transistor and the second transistor is a high-threshold transistor, and each of the third transistor and the fourth transistor is a low-threshold transistor, and wherein a threshold-voltage of the high-threshold transistor is larger than a threshold-voltage of the low-threshold transistor. ### Claim 19 (depends on 18) The integrated circuit of claim 18, further comprising: a first conductive segment extending in the second direction and intersecting with the active zone at a first intersection between the first channel regions and the second channel regions; a second conductive segment extending in the second direction and intersecting with the active zone at a second intersection, wherein both the first channel regions and the third channel regions are between the second intersection and the first intersection in the active zone; and a routing line, extending in the first direction, conductively connecting to each gate-strip in the plurality of gate-strips through a type-one via and conductively connecting to the second conductive segment through a type-two via. ### Claim 20 (depends on 19) The integrated circuit of claim 19, further comprising: a third conductive segment extending in the second direction and intersecting with the active zone at a third intersection, wherein both the second channel regions and the fourth channel regions are between the third intersection and the first intersection in the active zone.