# US 11,309,302 B2 · Manufacturing method of semiconductor package including thermal conductive block

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- Number: US 11,309,302 B2
- Document ID: US11309302B2
- Status: Granted
- Kind: B2
- Application number: 16/898,409
- Filed: 2020-06-10
- Published: 2020-09-24
- Granted: 2022-04-19
- Earliest claimed: 2018-08-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Shih-Wei Chen; Chih-Hua Chen; Hsin-Yu Pan; Hao-Yi Tsai; Lipu Kris Chuang; Tin-Hao Kuo
- Web page: https://patentgrep.com/patent/US11309302B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 90/00: Package configurations
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 40/00: Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/30: Die-attach connectors
- H10W 72/50: Bond wires
- H10W 72/90: Bond pads, in general
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/016: {using moulds}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/652: Cross-sectional shapes
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/354: {comprising polymers}
- H10W 72/551: {Materials of bond wires}
- H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)}
- H10W 72/879: {Bump connectors and bond wires}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Manufacturing method of semiconductor package includes following steps. Bottom package is provided. The bottom package includes a die and a redistribution structure electrically connected to die. A first top package and a second top package are disposed on a surface of the redistribution structure further away from the die. An underfill is formed into the space between the first and second top packages and between the first and second top packages and the bottom package. The underfill covers at least a side surface of the first top package and a side surface of the second top package. A hole is opened in the underfill within an area overlapping with the die between the side surface of the first top package and the side surface of the second top package. A thermally conductive block is formed in the hole by filling the hole with a thermally conductive material.

## Claims

### Claim 1

A manufacturing method of a semiconductor package, comprising:
providing a bottom package, wherein the bottom package includes a die and a redistribution structure electrically connected to the die;
disposing a first top package, a conductive ball and a second top package on a surface of the redistribution structure further away from the die;
filling an underfill into a space between the first and second top packages and between the first and second top packages and the bottom package, wherein the underfill covers a side surface of the first top package and a side surface of the second top package;
opening a hole in the underfill within an area overlapping with the die between the side surface of the first top package and the side surface of the second top package, wherein the hole exposes the conductive ball; and
forming a thermally conductive block in the hole by filling the hole with a thermally conductive material.

### Claim 2 (depends on 1)

The method of claim 1, wherein the conductive ball is connected to a conductive ground plane of the redistribution structure.

### Claim 3 (depends on 1)

The method of claim 1, wherein filling the hole with a thermally conductive material further comprises applying the thermally conductive material over top surfaces of the first and second top packages and into the hole.

### Claim 4 (depends on 1)

The method of claim 1, wherein opening the hole comprises performing laser drilling.

### Claim 5 (depends on 1)

The method of claim 1, wherein forming the thermally conductive block further comprises curing the thermally conductive material.

### Claim 6 (depends on 1)

The method of claim 1, further comprising forming an adhesion layer in the hole and on the first and second top packages before forming a thermally conductive block in the hole.

### Claim 7

A manufacturing method of a semiconductor package, comprising:
providing a bottom package comprising a semiconductor die and a ground plane;
disposing a top package on the bottom package, the top package being electrically connected to the semiconductor die of the bottom package by a plurality of conductive balls;
disposing an underfill between the top package and the bottom package, wherein the underfill surrounds the conductive balls and is further disposed on a side of the top package;
removing a portion of the underfill to form a hole at the side of the top package exposing the ground plane;
forming an electrically conductive adhesion layer on the top package and in the hole, and the electrically conductive adhesion being in contact with the exposed ground plane;
disposing a thermally conductive material within the hole and over the top package; and
curing the thermally conductive material disposed within the hole and over the top package.

### Claim 8 (depends on 7)

The method of claim 7, wherein the electrically conductive adhesion layer is conformally formed in the hole and on the top package before disposing the thermally conductive material.

### Claim 9 (depends on 8)

The method of claim 8, wherein the electrically conductive adhesion layer includes at least one material selected from copper, tantalum, and titanium-copper alloys.

### Claim 10 (depends on 7)

The method of claim 7, wherein the thermally conductive material includes a thermally conductive paste.

### Claim 11 (depends on 7)

The method of claim 7, wherein, after curing, the thermally conductive material disposed over the top package forms a cap portion, and the thermally conductive material disposed within the hole forms a thermal relaxation block extending from the cap portion towards the bottom package.

### Claim 12 (depends on 7)

The method of claim 7, wherein the top package is one of a plurality of top packages which are disposed on the bottom package.

### Claim 13 (depends on 7)

The method of claim 7, wherein providing the bottom package comprises:
forming a first redistribution structure,
disposing the semiconductor die on the first redistribution structure;
forming conductive structures on the first redistribution structure;
encapsulating the semiconductor die and the conductive structures in an encapsulant; and
forming a second redistribution structure on the encapsulated semiconductor die,
wherein the first redistribution structure is electrically connected to the encapsulated semiconductor die via the conductive structures and the second redistribution structure, and the top package is disposed on the first redistribution structure.

### Claim 14

A manufacturing method of a semiconductor package, comprising:
forming a redistribution structure, the redistribution structure being electrically connected to an encapsulated semiconductor die;
connecting a first package and a second package to the redistribution structure via conductive balls, the first package and the second package being separated from each other by a gap;
disposing an electrically conductive adhesion layer over the redistribution structure, on the first package and the second package, and in the gap;
applying a thermally conductive material on the electrically conductive adhesion layer; and
curing the thermally conductive material after the thermally conductive material is applied on the electrically conductive adhesion layer.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
forming an underfill in the gap between the first package and the second package, wherein the underfill at least partially covers facing side surfaces of the first package and the second package; and
removing a portion of the underfill from the gap before disposing the electrically conductive adhesion layer,
wherein a remaining portion of the underfill is disposed between the electrically conductive adhesion layer and the facing side surfaces of the first package and the second package.

### Claim 16 (depends on 15)

The method of claim 15, wherein the redistribution structure comprises a conductive ground plane, and the method further comprises removing a portion of the redistribution structure to expose the conductive ground plane.

### Claim 17 (depends on 16)

The method of claim 16, wherein the portion of the redistribution structure and the portion of the underfill are removed via laser drilling.

### Claim 18 (depends on 16)

The method of claim 16, wherein the encapsulated semiconductor die is partially exposed after removal of the portion of the redistribution structure.

### Claim 19 (depends on 14)

The method of claim 14, further comprising connecting an additional conductive ball to the redistribution structure beside the conductive balls connecting the first package and the second package to the redistribution structure, wherein the electrically conductive adhesion layer is further disposed on the additional conductive ball.

### Claim 20 (depends on 11)

The method of claim 11, further comprising attaching a heat spreader on the cap portion.