# US 11,309,301 B2 · Stacked die assembly including double-sided inter-die bonding connections and methods of forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,301 B2 - Document ID: US11309301B2 - Status: Granted - Kind: B2 - Application number: 16/886,221 - Filed: 2020-05-28 - Published: 2021-12-02 - Granted: 2022-04-19 - Earliest claimed: 2020-05-28 - Assignees: SanDisk Technologies LLC - Applicants: Sandisk Technologies LLC - Inventors: Fei Zhou; Raghuveer S. Makala; Rahul Sharangpani; Adarsh Rajashekhar - Web page: https://patentgrep.com/patent/US11309301B2 ## CPC - H10W 90/00: Package configurations - H10W 80/00: Direct bonding of chips, wafers or substrates - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping} - H10W 72/07554: {changes in dispositions} - H10W 72/354: {comprising polymers} - H10W 72/547: {Dispositions of multiple bond wires} - H10W 72/59: Bond pads specially adapted therefor - H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)} - H10W 72/859: {Bump connectors and bond wires} - H10W 72/865: {Die-attach connectors and bond wires} - H10W 72/874: {On different surfaces} - H10W 72/90: Bond pads, in general - H10W 72/934: {Cross-sectional shape, i.e. in side view} - H10W 72/944: {Dispositions of multiple bond pads} - H10W 80/732: {having shape changed during the connecting} - H10W 80/743: {having disposition changed during the connecting} - H10W 90/20: Configurations of stacked chips - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/752: {between stacked chips} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/792: {between multiple chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES ## Abstract Multiple bonded units are provided, each of which includes a respective front-side die and a backside die. The two dies in each bonded unit may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The multiple bonded units can be attached such that front-side external bonding pads have physically exposed surfaces that face upward and backside external bonding pads of each bonded unit have physically exposed surfaces that face downward. A first set of bonding wires can connect a respective pair of front-side external bonding pads, and a second set of bonding wires can connect a respective pair of backside external bonding pads. ## Claims ### Claim 1 A structure comprising a stacked die assembly, wherein the stacked die assembly comprises: a vertical stack of bonded units, wherein each bonded unit comprises a respective front-side semiconductor die including front-side external bonding pads and a respective backside semiconductor die including backside external bonding pads, wherein the respective backside semiconductor die is bonded to the respective front-side semiconductor die, and wherein the front-side external bonding pads of each bonded unit have physically exposed surfaces that face upward and the backside external bonding pads of each bonded unit have physically exposed surfaces that face downward; a first set of bonding wires connecting the front-side external bonding pads; and a second set of bonding wires connecting the backside external bonding pads. ### Claim 2 (depends on 1) The structure of claim 1, wherein each front-side semiconductor die further comprises a front-side memory array and each backside semiconductor die further comprises a backside memory array. ### Claim 3 (depends on 2) The structure of claim 2, wherein: the front-side semiconductor die within each bonded unit comprises front-side metal interconnect structures embedded in front-side dielectric material layers, wherein a subset of the front-side metal interconnect structures is connected to the front-side external bonding pads within each bonded unit; and the backside semiconductor die within each bonded unit comprises backside metal interconnect structures embedded in backside dielectric material layers, wherein a subset of the backside metal interconnect structures is connected to the backside external bonding pads within each bonded unit. ### Claim 4 (depends on 1) The structure of claim 1, wherein: the front-side semiconductor die within each bonded unit comprises a front-side substrate; the backside semiconductor die within each bonded unit comprises a backside substrate; and the front-side substrate is bonded to the backside substrate. ### Claim 5 (depends on 4) The structure of claim 4, wherein the backside semiconductor die and the front-side semiconductor die in the same bonded unit are not directly electrically connected to each other. ### Claim 6 (depends on 1) The structure of claim 1, wherein: each vertically neighboring pair of bonded units comprises an overlying bonded unit and an underlying bonded unit; and the overlying bonded unit is laterally offset along a first horizontal direction relative to the underlying bonded unit. ### Claim 7 (depends on 6) The structure of claim 6, wherein: front-side external bonding pads within each front-side semiconductor die are laterally offset from an edge of the front-side semiconductor die by a uniform lateral offset distance along the first horizontal direction; and the edge of the respective front-side semiconductor die laterally extends along a second horizontal direction that is perpendicular to the first horizontal direction. ### Claim 8 (depends on 6) The structure of claim 6, wherein: backside external bonding pads within each backside semiconductor die are laterally offset from an edge of the backside semiconductor die by a uniform lateral offset distance; and the edge of the backside semiconductor die laterally extends along a second horizontal direction that is perpendicular to the first horizontal direction. ### Claim 9 (depends on 1) The structure of claim 1, wherein: each front-side external bonding pad within the stacked die assembly does not have an areal overlap with any overlying bonded unit within the stacked die assembly in a plan view along a direction along which the bonded units are stacked; and each backside external bonding pad within the stacked die assembly does not have an areal overlap with any underlying bonded unit within the stacked die assembly in the plan view. ### Claim 10 (depends on 1) The structure of claim 1, wherein each vertically neighboring pair of bonded units is attached to each other by a respective adhesive layer. ### Claim 11 (depends on 10) The structure of claim 10, further comprising: a mounting substrate on which the vertical stack of bonded units is mounted by an additional adhesive layer; and additional bonding wires providing electrical connection between bonding pads located on the mounting substrate and front-side external bonding pads and backside external bonding pads of a most proximal bonded unit among the bonded units of the stacked die assembly. ### Claim 12 (depends on 1) The structure of claim 1, wherein each of the front-side semiconductor dies and the backside semiconductor dies further comprises: a respective logic circuit including semiconductor devices located on a respective substrate and configured to control operation of memory elements within the respective memory array; and respective metal interconnect structures embedded in respective dielectric material layers and providing electrical connection between the semiconductor devices of the respective logic circuit and the memory elements within the respective memory array. ### Claim 13 (depends on 12) The structure of claim 12, wherein the respective memory array comprises: a vertically alternating stack of insulating layers and electrically conductive layers; a plurality of memory opening fill structures each including a respective vertical semiconductor channel and a respective vertical stack of memory elements located at levels of the electrically conductive layers; bit lines electrically connected to a respective subset of the plurality of memory opening fill structures; a stepped dielectric material portion located on stepped surfaces of the alternating stack; and layer contact via structures vertically extending through the stepped dielectric material portion and contacting a respective one of the electrically conductive layers. ### Claim 14 A method of forming a structure including a stacked die assembly, the method comprising: providing multiple bonded units, wherein each bonded unit comprises a respective front-side semiconductor die including front-side external bonding pads and a respective backside semiconductor die including backside external bonding pads, wherein the respective backside semiconductor die is bonded to the respective front-side semiconductor die; forming a vertical stack of the multiple bonded units by attaching the multiple bonded units to each other such that the front-side external bonding pads of each bonded unit have physically exposed surfaces that face upward and the backside external bonding pads of each bonded unit have physically exposed surfaces that face downward; forming a first set of bonding wires that connect a respective pair of front-side external bonding pads; and forming a second set of bonding wires that connect a respective pair of backside external bonding pads. ### Claim 15 (depends on 14) The method of claim 14, wherein the front-side semiconductor die further comprises a front-side memory array and the backside semiconductor die further comprises a backside memory array. ### Claim 16 (depends on 15) The method of claim 15, wherein: the front-side semiconductor die within each bonded unit comprises a front-side substrate; the backside semiconductor die within each bonded unit comprises a backside substrate; and the front-side substrate is bonded to the backside substrate. ### Claim 17 (depends on 16) The method of claim 16, wherein the backside semiconductor die and the front-side semiconductor die in the same bonded unit are not directly electrically connected to each other. ### Claim 18 (depends on 14) The structure of claim 14, wherein the multiple bonded units are staggered such that each overlying bonded unit is laterally offset along a first horizontal direction relative to an underlying bonded unit. ### Claim 19 (depends on 14) The method of claim 14, further comprising forming the vertical stack of the multiple bonded units by attaching vertically neighboring pairs of bonded units employing adhesive layers. ### Claim 20 (depends on 19) The method of claim 19, further comprising: attaching a mounting substrate to the vertical stack of the multiple bonded units employing an additional adhesive layer; and electrically connecting the vertical stack of the multiple bonded units to the mounting substrate by attaching additional bonding wires to bonding pads located on the mounting substrate and to front-side external bonding pads or backside external bonding pads of a most proximal bonded unit among the vertical stack of the multiple bonded units.