# US 11,309,300 B2 · Semiconductor package including processor chip and memory chip

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- Number: US 11,309,300 B2
- Document ID: US11309300B2
- Status: Granted
- Kind: B2
- Application number: 16/051,926
- Filed: 2018-08-01
- Published: 2019-05-16
- Granted: 2022-04-19
- Earliest claimed: 2017-11-13
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Kil-soo Kim
- Web page: https://patentgrep.com/patent/US11309300B2

## CPC

- H10W 90/00: Package configurations
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 70/63: Vias, e.g. via plugs
- H10W 72/01: {Manufacture or treatment}
- H10W 72/07354: {changes in dispositions}
- H10W 72/07532: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07533: {Ultrasonic bonding, e.g. thermosonic bonding}
- H10W 72/07554: {changes in dispositions}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/547: {Dispositions of multiple bond wires}
- H10W 72/552: {comprising metals or metalloids, e.g. silver}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/5525: {comprising copper [Cu]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/865: {Die-attach connectors and bond wires}
- H10W 72/879: {Bump connectors and bond wires}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/753: {between laterally-adjacent chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/755: {between a chip and a laterally-adjacent insulating package substrate, interpose or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls.

## Claims

### Claim 1

A semiconductor package, comprising:
a package substrate;
a processor chip mounted on a first region of the package substrate;
a plurality of memory chips mounted on a second region of the package substrate, the second region of the package substrate being spaced apart from the first region of the package substrate;
a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, the processor chip and the signal transmission device transmit a signal therebetween via the package substrate; and
a plurality of first bonding wires that connect the plurality of memory chips directly to the signal transmission device, the plurality of memory chips and the signal transmission device transmit a signal therebetween via the plurality of first bonding wires without passing via the package substrate,
wherein the signal transmission device includes:
upper pads in an upper surface portion of the signal transmission device, the upper pads connected to the plurality of first bonding wires;
penetrating electrodes in a main body portion of the signal transmission device, the penetrating electrodes connected to the upper pads; and
lower pads in a lower surface portion of the signal transmission device, the lower pads connected to the penetrating electrodes and connected to the package substrate via bonding balls.

### Claim 2 (depends on 1)

The semiconductor package as claimed in claim 1, further comprising:
a second bonding wire that directly connects the plurality of memory chips to the package substrate.

### Claim 3 (depends on 2)

The semiconductor package as claimed in claim 2, wherein:
the plurality of memory chips include an input/output (I/O) pad and a power/ground pad,
the plurality of first bonding wires are connected to the I/O pad, and
the second bonding wire is connected to the power/ground pad.

### Claim 4 (depends on 2)

The semiconductor package as claimed in claim 2, wherein the second bonding wire connects a memory chip at a lowest position among the plurality of memory chips to the package substrate and connects the plurality of memory chips to one another.

### Claim 5 (depends on 1)

The semiconductor package as claimed in claim 1, wherein
each of the plurality of memory chips includes:
a semiconductor substrate having an active surface and an inactive surface that face each other;
a memory device on the active surface; and
an upper memory bonding pad on the active surface, the upper memory bonding pad connected to the first bonding wires, and wherein
the plurality of memory chips are sequentially and horizontally shifted by a distance from each other and stacked such that the upper memory bonding pads are exposed.

### Claim 6 (depends on 5)

The semiconductor package as claimed in claim 5, wherein the memory chips are positioned horizontally farther from the processor chip as the memory chips are positioned vertically farther from the package substrate.

### Claim 7 (depends on 5)

The semiconductor package as claimed in claim 5, wherein the memory chips are positioned horizontally closer to the processor chip as the memory chips are positioned vertically farther from the package substrate.

### Claim 8 (depends on 7)

The semiconductor package as claimed in claim 7, wherein in a plan view, a plane area of the signal transmission device is less than a plane area of at least one of the plurality of memory chips, and a portion of the signal transmission device overlaps the at least one of the plurality of memory chips.

### Claim 9 (depends on 1)

The semiconductor package as claimed in claim 1, wherein the signal transmission device further includes a buffer circuit to control a capacitance loading of the plurality of memory chips.

### Claim 10

A semiconductor package, comprising:
a package substrate;
a processor chip mounted on the package substrate;
a plurality of memory chips mounted on the package substrate and to exchange data with each other;
a signal transmission device mounted on the package substrate, the processor chip and the signal transmission device transmit a signal therebetween via the package substrate;
a plurality of first bonding wires that connect the plurality of memory chips directly to the signal transmission device, the plurality of memory chips and the signal transmission device transmit a signal therebetween via the plurality of first bonding wires without passing via the package substrate; and
a molding member that covers lateral surfaces of the processor chip, the plurality of memory chips, and the signal transmission device, wherein:
the processor chip, the plurality of memory chips, and the signal transmission device are spaced apart from each other, and
the signal transmission device includes:
upper pads in an upper surface portion of the signal transmission device, the upper pads connected to the plurality of first bonding wires;
penetrating electrodes in a main body portion of the signal transmission device, the penetrating electrodes connected to the upper pads; and
lower pads in a lower surface portion of the signal transmission device, the lower pads connected to the penetrating electrodes and connected to the package substrate via bonding balls.

### Claim 11 (depends on 10)

The semiconductor package as claimed in claim 10, wherein:
the plurality of memory chips are identical, and
at least two of the plurality of first bonding wires are connected to a single upper pad of the signal transmission device.

### Claim 12 (depends on 10)

The semiconductor package as claimed in claim 10, wherein:
the plurality of memory chips include upper memory bonding pads connected to the first bonding wires, and are sequentially and horizontally shifted by a distance from each other and stacked such that the upper memory bonding pads are exposed, and
the plurality of first bonding wires connect the upper memory bonding pad of a memory chip at a lowest position among the plurality of memory chips to the upper pads of the signal transmission device and connect the upper memory bonding pads of the plurality of memory chips to each other.

### Claim 13 (depends on 10)

The semiconductor package as claimed in claim 10, wherein:
the plurality of memory chips include upper memory bonding pads, and are sequentially and horizontally shifted by a distance from each other and stacked such that the upper memory bonding pads are exposed,
a memory chip at a highest position among the plurality of memory chips further includes redistribution pads connected to the first bonding wires,
the semiconductor package further includes a third bonding wire that connects the upper memory bonding pads to each other.

### Claim 14 (depends on 13)

The semiconductor package as claimed in claim 13, wherein the memory chip at the highest position further includes redistribution lines that electrically connect the upper memory bonding pads to the redistribution pads.