# US 11,309,296 B2 · Semiconductor package and manufacturing method thereof

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- Number: US 11,309,296 B2
- Document ID: US11309296B2
- Status: Granted
- Kind: B2
- Application number: 16/687,713
- Filed: 2019-11-19
- Published: 2020-03-19
- Granted: 2022-04-19
- Earliest claimed: 2017-09-26
- Assignees: Powertech Technology Inc.
- Applicants: Powertech Technology Inc.
- Inventors: Nan-Chun Lin; Hung-Hsin Hsu; Shang-Yu Chang Chien; Wen-Hsiung Chang
- Web page: https://patentgrep.com/patent/US11309296B2

## CPC

- H10W 74/01: Manufacture or treatment
- H10W 90/00: Package configurations
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/216: {characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 74/014: {using batch processing}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10P 72/7418: {of passive members, e.g. a chip mounting substrate}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10W 72/01: {Manufacture or treatment}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/354: {comprising polymers}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/20: Configurations of stacked chips
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/721: {of bump connectors}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package including a plurality of first chips, a plurality of through silicon vias, a least one insulator, a first circuit structure and a first encapsulant is provided. The first chip electrically connected to the through silicon vias includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending from the first back surface towards the first active surface. The insulator is disposed on the first active surfaces of the first chips. The first circuit structure disposed on the first back surfaces of the first chips and electrically connected to the through silicon vias. The first encapsulant, laterally encapsulating the first chips.

## Claims

### Claim 1

A manufacturing method of a semiconductor package, comprising:
providing a plurality of first chips, each of the first chips comprising a first active surface, a sensing area on the first active surface, a first back surface opposite to the first active surface and a plurality of through holes extending from the first back surface towards the first active surface;
forming a plurality of through silicon vias in the through holes of the first chip;
forming a first circuit structure on the first back surface of the first chip to electrically connect the through silicon vias;
providing a carrier;
providing at least one insulator;
bonding the carrier, the insulator, and the first chips with the through silicon vias and the first circuit structure, wherein the insulator is disposed between the carrier and the first chips, the first active surfaces of the first chips facing towards the insulator, and the first chips disposed on the carrier are physically separated from each other;
forming a first encapsulant on the carrier, wherein the first encapsulant laterally encapsulates the first chips; and
forming a second circuit structure on the first encapsulant,
wherein the second circuit structure is electrically connected to the first circuit structure,
wherein a portion of the first encapsulant is disposed between the first circuit structure and the second circuit structure,
wherein a projected area of the first circuit structure projected on the carrier is substantially equal to a projected area of the first chips projected on the carrier, and a projected area of the second circuit structure projected on the carrier is larger than the projected area of the first chips projected on the carrier.

### Claim 2 (depends on 1)

The manufacturing method according to claim 1, wherein the first chips comprise a first sensor chip and a second sensor chip, a photosensitive material included in the sensing area of the first sensor chip is different form a photosensitive material included in the sensing area of the second sensor chip.

### Claim 3 (depends on 1)

The manufacturing method according to claim 1, wherein the first encapsulant further laterally encapsulate the first circuit structure.

### Claim 4

A manufacturing method of a semiconductor package, comprising:
providing a plurality of first chips, each of the first chips comprising a first active surface, a sensing area on the first active surface, a first back surface opposite to the first active surface and a plurality of through holes extending from the first back surface towards the first active surface;
forming a plurality of through silicon vias in the through holes of the first chip;
forming a first circuit structure on the first back surface of the first chip to electrically connect the through silicon vias;
providing a carrier;
providing at least one insulator;
bonding the carrier, the insulator, and the first chips with the through silicon vias and the first circuit structure, wherein the insulator is disposed between the carrier and the first chips, the first active surfaces of the first chips facing towards the insulator, and the first chips disposed on the carrier are physically separated from each other;
forming a first encapsulant on the carrier, wherein the first encapsulant laterally encapsulates the first chips; and
forming a second circuit structure on the first encapsulant, wherein after forming the second circuit structure, the first chips are electrically connected to each other through the second circuit structure.

### Claim 5 (depends on 4)

The manufacturing method according to claim 4, wherein the first chips comprise a first sensor chip and a second sensor chip, a photosensitive material included in the sensing area of the first sensor chip is different form a photosensitive material included in the sensing area of the second sensor chip.

### Claim 6 (depends on 4)

The manufacturing method according to claim 4, wherein the first encapsulant further laterally encapsulate the first circuit structure.

### Claim 7

A semiconductor package, comprising:
a plurality of first chips, each of the first chips comprising a first active surface, a sensing area on the first active surface, a first back surface opposite to the first active surface and a plurality of through holes extending from the first back surface towards the first active surface;
a plurality of through silicon vias, disposed in the through holes of the first chips and electrically connected to the first chips;
at least one insulator, disposed on the first active surfaces of the first chips;
a first circuit structure, disposed on the first back surfaces of the first chips and electrically connected to the through silicon vias;
a first encapsulant, laterally encapsulating the first chips; and
a second circuit structure, electrically connected to the first circuit structure, wherein a portion of the first encapsulant is disposed between the first circuit structure and the second circuit structure, wherein a projected area of the first circuit structure projected on the permanent carrier is substantially equal to a projected area of the first chips projected on the permanent carrier, and a projected area of the second circuit structure projected on the permanent carrier is larger than the projected area of the first chips projected on the permanent carrier.

### Claim 8 (depends on 7)

The semiconductor package according to claim 7, wherein the first chips comprise a first sensor chip and a second sensor chip, a photosensitive material included in the sensing area of the first sensor chip is different form a photosensitive material included in the sensing area of the second sensor chip.

### Claim 9 (depends on 7)

The semiconductor package according to claim 7, wherein the first encapsulant further laterally encapsulate the insulator.

### Claim 10 (depends on 7)

The semiconductor package according to claim 7, further comprising:
a permanent carrier, wherein the insulator is disposed between the permanent carrier and the first chips.

### Claim 11 (depends on 7)

The semiconductor package according to claim 7, wherein the first encapsulant further laterally encapsulate the first circuit structure.

### Claim 12 (depends on 7)

The semiconductor package according to claim 7, further comprising:
only one second chip, disposed on the first circuit structure and comprising a second active surface facing towards the first back surfaces of the first chips, wherein the second chip is electrically connected to the first chips through the first circuit structure.

### Claim 13 (depends on 7)

The semiconductor package according to claim 7, wherein the first encapsulant is disposed on the insulator.