# US 11,309,292 B2 · 3D semiconductor device and structure with metal layers

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- Number: US 11,309,292 B2
- Document ID: US11309292B2
- Status: Granted
- Kind: B2
- Application number: 17/536,019
- Filed: 2021-11-27
- Published: 2022-03-17
- Granted: 2022-04-19
- Earliest claimed: 2012-12-22
- Assignees: Monolithic 3D Inc.
- Applicants: Monolithic 3D Inc.
- Inventors: Zvi Or-Bach; Brian Cronquist
- Web page: https://patentgrep.com/patent/US11309292B2

## CPC

- H10D 88/01: {Manufacture or treatment}
- H10W 90/00: Package configurations
- H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells}
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/027: {by etching at gate locations}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 86/01: Manufacture or treatment
- H10D 86/011: {comprising FinFETs}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 86/215: {comprising FinFETs}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10W 20/021: {of interconnections within wafers or substrates}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/845: {the switching components being connected to a common vertical conductor}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device, the device including: a first silicon layer including a first single crystal silicon; a first metal layer over the first silicon layer; a second metal layer over the first metal layer; a first level including a plurality of transistors over the second metal layer, where the plurality of transistors include a second single crystal silicon; a third metal layer over the first level; a fourth metal layer over the third metal layer, where the fourth metal layer is aligned to the first metal layer with less than 40 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm.

## Claims

### Claim 1

A semiconductor device, the device comprising:
a first silicon layer comprising a first single crystal silicon;
a first metal layer over said first silicon layer;
a second metal layer over said first metal layer;
a first level comprising a plurality of transistors, said first level over said second metal layer,
wherein said plurality of transistors comprise a second single crystal silicon;
a third metal layer over said first level;
a fourth metal layer over said third metal layer,
wherein said fourth metal layer is aligned to said first metal layer with less than 40 nm alignment error; and
a via disposed through said first level,
wherein said via has a diameter of less than 450 nm.

### Claim 2 (depends on 1)

The device according to claim 1,
wherein said via comprises tungsten.

### Claim 3 (depends on 1)

The device according to claim 1,
wherein said first level thickness is less than two microns.

### Claim 4 (depends on 1)

The device according to claim 1, further comprising:
connection pads disposed over portions of said fourth metal layer,
wherein said connection pads are capable to provide connections to external devices.

### Claim 5 (depends on 1)

The device according to claim 1, further comprising:
a global power distribution network and a local power distribution network,
wherein said global power distribution network comprises said fourth metal layer, and
wherein said local power distribution network comprises said third metal layer.

### Claim 6 (depends on 1)

The device according to claim 1,
wherein at least one of said transistors comprise a two sided gate.

### Claim 7 (depends on 1)

The device according to claim 1, further comprising:
oxide to oxide bonds.

### Claim 8

A semiconductor device, the device comprising:
a first silicon layer comprising first single crystal silicon;
a first metal layer over said first silicon layer;
a second metal layer over said first metal layer;
a first level comprising a plurality of transistors, said first level over said second metal layer,
wherein said plurality of transistors comprise second single crystal silicon;
a third metal layer over said first level;
a fourth metal layer over said third metal layer,
wherein said fourth metal layer is aligned to said first metal layer with less than 40 nm alignment error; and
a via disposed through said first level,
wherein said via comprises tungsten.

### Claim 9 (depends on 8)

The device according to claim 8,
wherein said via has a diameter of less than 450 nm.

### Claim 10 (depends on 8)

The device according to claim 8,
wherein said first level has a thickness of less than two microns.

### Claim 11 (depends on 8)

The device according to claim 8, further comprising:
connection pads over a portion of said fourth metal layer,
wherein said connection pads are capable to provide connection to external devices.

### Claim 12 (depends on 8)

The device according to claim 8, further comprising:
a global power distribution network and a local power distribution network
wherein said global power distribution network comprises said fourth metal layer, and
wherein said local power distribution network comprises said third metal layer.

### Claim 13 (depends on 8)

The device according to claim 8,
wherein at least one of said transistors comprises a two sided gate.

### Claim 14 (depends on 8)

The device according to claim 8, further comprising:
oxide to oxide bonds.

### Claim 15

A semiconductor device, the device comprising:
a first silicon layer comprising first single crystal silicon;
a first metal layer over said first silicon layer;
a second metal layer over said first metal layer;
a first level comprising a plurality of transistors, said first level over said second metal layer,
wherein said plurality of transistors comprise second single crystal silicon;
a third metal layer over said first level;
a fourth metal layer over said third metal layer,
wherein said fourth metal layer is aligned to said first metal layer with less than 40 nm alignment error;
a global power distribution network and a local power distribution network,
wherein said global power distribution network comprises said fourth metal layer, and
wherein said local power distribution network comprises said third metal layer.

### Claim 16 (depends on 15)

The device according to claim 15, further comprising:
a via disposed through said first level,
wherein said via comprises tungsten.

### Claim 17 (depends on 15)

The device according to claim 15,
wherein said first level has a thickness of less than two microns.

### Claim 18 (depends on 15)

The device according to claim 15, further comprising:
connection pads disposed over said fourth metal layer,
wherein said connection pads are capable to provide connection to external devices.

### Claim 19 (depends on 15)

The device according to claim 15,
wherein at least one of said transistors comprise a two sided gate.

### Claim 20 (depends on 15)

The device according to claim 15, further comprising:
a via through said first level,
wherein said via has a diameter of less than 450 nm.