# US 11,309,291 B2 · Die stack structure and manufacturing method thereof

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- Number: US 11,309,291 B2
- Document ID: US11309291B2
- Status: Granted
- Kind: B2
- Application number: 17/026,274
- Filed: 2020-09-20
- Published: 2022-03-24
- Granted: 2022-04-19
- Earliest claimed: 2020-09-20
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Hsien-Wei Chen; Jie Chen; Ming-Fa Chen; Sung-Feng Yeh; Ying-Ju Chen
- Web page: https://patentgrep.com/patent/US11309291B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 90/00: Package configurations
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/90: Bond pads, in general
- H10W 74/01: Manufacture or treatment
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7434: {used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/0198: {batch processes}
- H10W 72/07331: {Connecting techniques}
- H10W 72/07354: {changes in dispositions}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/951: {Materials of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 80/211: {using auxiliary members, e.g. aids for protecting the bonding area}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/743: {having disposition changed during the connecting}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/732: {between stacked chips}
- H10W 90/792: {between multiple chips}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A die stack structure includes an interconnection structure, a logic die, a control die, a first insulating encapsulant, a dummy die, a memory cube and a second insulating encapsulant. The logic die is electrically connected to the interconnection structure. The logic die comprises a first dielectric bonding structure. The control die is laterally separated from the logic die and electrically connected to the interconnection structure. The first insulating encapsulant laterally encapsulates the logic die and the control die. The dummy die is stacked on the logic die, the logic die is located between the interconnection structure and the dummy die, the dummy die comprises a second dielectric bonding structure, and a bonding interface is located between the first dielectric bonding structure and the second dielectric bonding structure. The memory cube is stacked on and electrically connected to the control die, wherein the control die is located between the interconnection structure and the memory cube. The second insulating encapsulant laterally encapsulates the dummy die and the memory cube.

## Claims

### Claim 1

A die stack structure, comprising:
an interconnection structure;
a logic die electrically connected to the interconnection structure, wherein the logic die comprises a first dielectric bonding structure;
a control die laterally separated from the logic die and electrically connected to the interconnection structure;
a first insulating encapsulant laterally encapsulating the logic die and the control die;
a dummy die stacked on the logic die, wherein the logic die is located between the interconnection structure and the dummy die, the dummy die comprises a second dielectric bonding structure, and a bonding interface is located between the first dielectric bonding structure and the second dielectric bonding structure;
a memory cube stacked on and electrically connected to the control die, wherein the control die is located between the interconnection structure and the memory cube; and
a second insulating encapsulant laterally encapsulating the dummy die and the memory cube.

### Claim 2 (depends on 1)

The die stack structure of claim 1, wherein a thickness of the logic die, a thickness of the control die and a thickness of the first insulating encapsulant are substantially the same as one another, and a thickness of the dummy die, a thickness of the memory cube and a thickness of the second insulating encapsulant are substantially the same as one another.

### Claim 3 (depends on 1)

The die stack structure of claim 1, wherein the bonding interface is a fusion bonding interface.

### Claim 4 (depends on 1)

The die stack structure of claim 1, wherein the dummy die is electrically isolated from the logic die, the control die, the memory cube and the interconnection structure.

### Claim 5 (depends on 1)

The die stack structure of claim 1, further comprising:
conductive elements, located on and electrically connected to the interconnection structure, wherein the interconnection structure is located between the conductive elements and the first insulating encapsulant.

### Claim 6

A die stack structure, comprising:
an interconnection structure comprising a first bonding structure;
a logic die stacked on the interconnection structure and comprising a second bonding structure, wherein the logic die is electrically connected to the interconnection structure by the second bonding structure and the first bonding structure, and a first hybrid bonding interface is located between the second bonding structure and the first bonding structure;
a control die stacked on the interconnection structure and comprising a third bonding structure, wherein the control die is electrically connected to the interconnection structure by the third bonding structure and the first bonding structure, the first hybrid bonding interface is located between the third bonding structure and the first bonding structure, and the control die and the logic die are disposed side-by-side;
a first insulating encapsulant laterally encapsulating the logic die and the control die;
a dummy die stacked on the logic die;
a memory cube stacked on and electrically connected to the control die; and
a second insulating encapsulant laterally encapsulating the dummy die and the memory cube.

### Claim 7 (depends on 6)

The die stack structure of claim 6, wherein the control die comprises a fourth bonding structure disposed opposite to the third bonding structure, the memory cube comprises a fifth bonding structure, the memory cube is electrically connected to the control die by the fifth bonding structure and the fourth bonding structure, and a second hybrid bonding interface is located between the fifth bonding structure and the fourth bonding structure.

### Claim 8 (depends on 7)

The die stack structure of claim 7, wherein the logic die comprises a sixth bonding structure disposed opposite to the second bonding structure, the dummy die comprises a seventh bonding structure, a bonding interface is located between the seventh bonding structure and the sixth bonding structure, and the bonding interface is substantially coplanar with the second hybrid bonding interface.

### Claim 9 (depends on 8)

The die stack structure of claim 8, wherein the seventh bonding structure comprises a die attach film (DAF).

### Claim 10 (depends on 6)

The die stack structure of claim 6, wherein a material of the first insulating encapsulant is different from a material of the second insulating encapsulant.

### Claim 11 (depends on 6)

The die stack structure of claim 6, wherein a material of the first insulating encapsulant is the same as a material of the second insulating encapsulant.

### Claim 12 (depends on 6)

The die stack structure of claim 6, wherein the second insulating encapsulate comprises a molding layer and a liner layer, the liner layer is located between the dummy die and the molding layer and between the memory cube and the molding layer, and a material of the molding layer is different form a material of the liner layer.

### Claim 13 (depends on 6)

The die stack structure of claim 6, wherein the memory cube comprises a plurality of memory dies sequentially stacked on the control die, the dummy die comprises a plurality of dummy blocks sequentially stacked on the logic die, and a thickness of the dummy die is substantially equal to a thickness of the memory cube.

### Claim 14 (depends on 6)

The die stack structure of claim 6, wherein a span of the dummy die is different from a span of the logic die.

### Claim 15 (depends on 6)

The die stack structure of claim 6, wherein the dummy die comprises a bulk semiconductor material free of an electronic device.

### Claim 16

A manufacturing method of a die stack structure, comprising:
forming an interconnection structure on a semiconductor substrate;
electrically connecting a logic die and a control die to the interconnection structure through a hybrid bonding process;
bonding a dummy die to the logic die;
electrically connecting a memory cube to the control die through another hybrid bonding process;
performing a encapsulating process to encapsulate the logic die, the control die, the dummy die and the memory cube;
removing the semiconductor substrate from the interconnection structure; and
performing a singulation process to dice the interconnection structure to form the die stack structure.

### Claim 17 (depends on 16)

The manufacturing method of claim 16, wherein before bonding the dummy die to the logic die and electrically connecting the memory cube to the control die, further comprising:
removing portions of the logic die and the control die to form a first recess in the logic die and a second recess in the control die; and
forming a first bonding film in the first recess and a second bonding film in the second recess.

### Claim 18 (depends on 16)

The manufacturing method of claim 16, wherein the dummy die is bonded to the logic die through a fusion bonding process.

### Claim 19 (depends on 16)

The manufacturing method of claim 16, wherein performing the encapsulating process to encapsulate the logic die, the control die, the dummy die and the memory cube comprises:
encapsulating the logic die and the control die by a first insulating encapsulant before bonding the dummy die to the logic die and electrically connecting the memory cube to the control die; and
encapsulating the dummy die and the memory cube by a second insulating encapsulant after bonding the dummy die to the logic die and electrically connecting the memory cube to the control die, wherein a material of the first insulating encapsulant is different from a material of the second insulating encapsulant.

### Claim 20 (depends on 16)

The manufacturing method of claim 16, wherein after removing the semiconductor substrate and before performing the singulation process, further comprising:
forming conductive elements on the interconnection structure and opposite to the logic die.