# US 11,309,290 B2 · Semiconductor apparatus including penetration electrodes connecting laminated semiconductor chips

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- Number: US 11,309,290 B2
- Document ID: US11309290B2
- Status: Granted
- Kind: B2
- Application number: 17/024,828
- Filed: 2020-09-18
- Published: 2021-04-08
- Granted: 2022-04-19
- Earliest claimed: 2019-10-04
- Assignees: Honda Motor Co., Ltd.; Tokyo Institute of Technology
- Applicants: Honda Motor Co., Ltd.; Tokyo Institute of Technology
- Inventors: Koji Sakui; Takayuki Ohba
- Web page: https://patentgrep.com/patent/US11309290B2

## CPC

- H10W 90/00: Package configurations
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 72/9226: {with via interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor apparatus according to an embodiment of the present invention includes: a plurality of semiconductor chips that are laminated; and a plurality of penetration electrodes that penetrate in a lamination direction through the plurality of semiconductor chips and that electrically connect together the plurality of semiconductor chips, wherein a semiconductor chip has at least one sub-memory array, and a penetration electrode penetrates through an outer circumferential part of the sub-memory array.

## Claims

### Claim 1

A semiconductor apparatus comprising:
a plurality of semiconductor chips that are laminated; and
a plurality of penetration electrodes that penetrate in a lamination direction through the plurality of semiconductor chips and that electrically connect together the plurality of semiconductor chips,
wherein a semiconductor chip of the plurality of semiconductor chips has at least one sub-memory array,
a penetration electrode of the plurality of penetration electrodes penetrates through an outer circumferential part of the sub-memory array, and
in the semiconductor chip, positions at which the penetration electrode penetrates are distributed so as to constitute a plurality of rows along the outer circumferential part.

### Claim 2 (depends on 1)

The semiconductor apparatus according to claim 1,
wherein the plurality of semiconductor chips are joined together via no bump.

### Claim 3 (depends on 1)

The semiconductor apparatus according to claim 1,
wherein a thickness of the semiconductor chip is greater than or equal to 2 μm and less than or equal to 10 μm.

### Claim 4

A semiconductor apparatus, comprising:
a plurality of semiconductor chips that are laminated; and
a plurality of penetration electrodes that penetrate in a lamination direction through the plurality of semiconductor chips and that electrically connect together the plurality of semiconductor chips,
wherein a semiconductor chip of the plurality of semiconductor chips has at least one sub-memory array,
a penetration electrode of the plurality of penetration electrodes penetrates through an outer circumferential part of the sub-memory array, and
the semiconductor chip has a replacement sub-memory array.

### Claim 5 (depends on 4)

The semiconductor apparatus according to claim 4,
wherein the plurality of semiconductor chips are joined together via no bump.

### Claim 6 (depends on 4)

The semiconductor apparatus according to claim 4,
wherein a thickness of the semiconductor chip is greater than or equal to 2 μm and less than or equal to 10 μm.