# US 11,309,286 B2 · Stack packages including a hybrid wire bonding structure

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- Number: US 11,309,286 B2
- Document ID: US11309286B2
- Status: Granted
- Kind: B2
- Application number: 16/590,724
- Filed: 2019-10-02
- Published: 2020-09-10
- Granted: 2022-04-19
- Earliest claimed: 2019-03-06
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Nam Jae Lee
- Web page: https://patentgrep.com/patent/US11309286B2

## CPC

- H10W 90/00: Package configurations
- H10W 72/075: {of bond wires}
- H10W 72/90: Bond pads, in general
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07553: {changes in shapes}
- H10W 72/07554: {changes in dispositions}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/537: {Multiple bond wires having different shapes}
- H10W 72/547: {Dispositions of multiple bond wires}
- H10W 72/853: {On the same surface}
- H10W 72/865: {Die-attach connectors and bond wires}
- H10W 72/874: {On different surfaces}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/983: {Reinforcing structures, e.g. collars}
- H10W 80/301: {Bonding techniques, e.g. hybrid bonding}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/20: Configurations of stacked chips
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A stack package includes first and second sub-chip stacks stacked on a package substrate and bonding wires. The first sub-chip stack includes first and second sub-chips. The first sub-chip has a first surface on which a first common pad is disposed. The second sub-chip has a third surface on which a second common pad is disposed. The third surface is bonded to the first surface such that the second common pad is bonded to the first common pad. The second sub-chip includes a fourth surface opposite to the second common pad and a through hole extending from the fourth surface to reveal the second common pad. The bonding wire is connected to the second common pad via the through hole and electrically connects both of the first and second common pads to the package substrate.

## Claims

### Claim 1

A stack package comprising:
a first sub-chip stack disposed on a package substrate;
a second sub-chip stack stacked on the first sub-chip stack to be laterally offset relative to the first sub-chip stack; and
bonding wires electrically connecting the first sub-chip stack to the package substrate,
wherein the first sub-chip stack comprises:
a first sub-chip having a first surface on which a first discrete pad and a first common pad are disposed; and
a second sub-chip having a third surface bonded to the first surface,
wherein the second sub-chip incudes:
a second discrete pad and a second common pad disposed on the third surface; and
through holes extending from a fourth surface of the second sub-chip opposite to the first sub-chip to reveal the first discrete pad, the second discrete pad and the second common pad,
wherein the second common pad is bonded to the first common pad, and
wherein each of the bonding wires passes through each of the through holes and is directly bonded to each of the first discrete pad, the second discrete pad and the second common pad.

### Claim 2 (depends on 1)

The stack package of claim 1, wherein the second sub-chip fully overlaps with the first sub-chip and is bonded to the first sub-chip.

### Claim 3 (depends on 1)

The stack package of claim 1, wherein the first discrete pad is disposed to be spaced apart from the second discrete pad to prevent the first discrete pad from vertically overlapping with the second discrete pad.

### Claim 4 (depends on 1)

The stack package of claim 1, wherein the first discrete pad and the second discrete pad are located at two opposite sides of the first common pad, respectively.

### Claim 5 (depends on 1)

The stack package of claim 1, wherein the first common pad is disposed to overlap with the second common pad.

### Claim 6 (depends on 1)

The stack package of claim 1,
wherein the through holes extend from the fourth surface of the second sub-chip to the third surface of the second sub-chip; and
wherein the through holes comprises:
a first through hole revealing the first discrete pad of the first sub-chip;
a second through hole penetrating the second sub-chip to reveal the second discrete pad; and
a third through hole penetrating the second sub-chip to reveal a backside surface of the second common pad opposite to first common pad.

### Claim 7 (depends on 6)

The stack package of claim 6, wherein the first through hole is deeper than the third through hole.

### Claim 8 (depends on 6)

The stack package of claim 6, wherein the bonding wires comprise:
a first bonding wire configured to be bonded to the first discrete pad via the first through hole and configured to electrically connect the first discrete pad to a first bonding finger of the package substrate;
a second bonding wire configured to be bonded to the second discrete pad via the second through hole and configured to electrically connect the second discrete pad to a second bonding finger of the package substrate; and
a third bonding wire configured to be bonded to the second common pad via the third through hole and configured to electrically connect the first and second common pads to a third bonding finger of the package substrate.

### Claim 9 (depends on 8)

The stack package of claim 8, further comprising a fourth bonding wire having one end which is bonded to the second common pad to be electrically connected to the third bonding wire and the other end which is electrically connected to the second sub-chip stack.

### Claim 10 (depends on 1)

The stack package of claim 1, further comprising a fifth bonding wire directly connecting the second sub-chip stack to the package substrate.

### Claim 11 (depends on 1)

The stack package of claim 1, wherein the first sub-chip and the second sub-chip have different thicknesses.

### Claim 12 (depends on 1)

The stack package of claim 1, wherein the second sub-chip has a thickness which is less than a thickness of the first sub-chip.

### Claim 13 (depends on 1)

The stack package of claim 1, wherein the second sub-chip stack has substantially the same shape as the first sub-chip stack.

### Claim 14 (depends on 1)

The stack package of claim 1, wherein the second sub-chip stack comprises:
a third sub-chip having a fifth surface on which a third discrete pad and a third common pad are disposed; and
a fourth sub-chip having a seventh surface bonded to the fifth surface,
wherein the fourth sub-chip comprises:
a fourth discrete pad and a fourth common pad disposed on the seventh surface; and
fourth through holes extending from an eighth surface of the fourth sub-chip opposite to the third sub-chip to reveal the third discrete pad, the fourth discrete pad and the fourth common pad.

### Claim 15 (depends on 1)

The stack package of claim 1, further comprising an adhesive layer attaching the second sub-chip to the first sub-chip.