# US 11,309,285 B2 · Three-dimensional stacking semiconductor assemblies and methods of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,285 B2 - Document ID: US11309285B2 - Status: Granted - Kind: B2 - Application number: 16/440,328 - Filed: 2019-06-13 - Published: 2020-12-17 - Granted: 2022-04-19 - Earliest claimed: 2019-06-13 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Owen R. Fay; Chan H. Yoo; Mark E. Tuttle - Web page: https://patentgrep.com/patent/US11309285B2 ## CPC - H10W 90/00: Package configurations - H10W 20/425: {Barrier, adhesion or liner layers} - H10W 72/0198: {batch processes} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 74/014: {using batch processing} - H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)} - H10W 70/652: Cross-sectional shapes - H10W 70/6528: {of the portions that connect to chips, wafers or package parts} - H10W 72/01: {Manufacture or treatment} - H10W 72/01323: {in liquid form, e.g. by dispensing droplets or by screen printing} - H10W 72/01336: {in solid form, e.g. by using a powder or by laminating a foil} - H10W 72/072: {of bump connectors} - H10W 72/07255: {changes in materials} - H10W 72/073: {of die-attach connectors} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 72/251: {Materials} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 90/20: Configurations of stacked chips - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Semiconductor device packages and associated assemblies are disclosed herein. In some embodiments, the semiconductor device package includes a substrate having a first side and a second side opposite the first side, a first metallization layer positioned at the first side of the substrate, and a second metallization layer in the substrate and electrically coupled to the first metallization layer. The semiconductor device package further includes a metal bump electrically coupled to the first metallization layer and a divot formed at the second side of the substrate and aligned with the metal bump. The divot exposes a portion of the second metallization layer and enables the portion to electrically couple to another semiconductor device package. ## Claims ### Claim 1 A semiconductor device package, comprising: a semiconductor substrate having an active side and an inactive side opposite the active side, the substrate including a first metallization layer positioned at the active side, a second metallization layer at least partially embedded in the substrate and electrically coupled directly to the first metallization layer and without using a through-silicon via (TSV), wherein the inactive side of the substrate includes a divot exposing a portion of the second metallization layer for providing a direct electrical connection between an external device and the second metallization layer; and a metal bump protruding away from the active side, directly aligned with the divot, and electrically coupled to the first metallization layer. ### Claim 2 (depends on 1) The semiconductor device package of claim 1, wherein the substrate has a depth not more than 15 μm. ### Claim 3 (depends on 1) The semiconductor device package of claim 1, wherein the substrate has a depth not more than 10 μm. ### Claim 4 (depends on 1) The semiconductor device package of claim 1, wherein the substrate has a depth not more than 5 μm. ### Claim 5 (depends on 1) The semiconductor device package of claim 1, wherein the semiconductor device package is a first semiconductor device package, and wherein the metal bump is configured to electrically couple circuitry on the active side of the first semiconductor device package to a second semiconductor device package without using the TSV when the second semiconductor device package is attached facing the inactive side. ### Claim 6 (depends on 1) The semiconductor device package of claim 1, wherein: the metal bump is a first metal bump, the first and second metallization layers are configured to provide one or more electrical connections across a thickness of the first semiconductor substrate measured between opposing surfaces, and the exposed portion of the second metallization layer is configured to directly attached to a second metal bump that is electrically coupled to a second semiconductor device package. ### Claim 7 (depends on 1) The semiconductor device package of claim 1, further comprising a passivation layer positioned at the active side of the substrate. ### Claim 8 A semiconductor device package, comprising: a semiconductor substrate having an active side and an inactive side opposite the active side, the substrate including a first metallization layer positioned at the active side, a second metallization layer at least partially embedded in the substrate and electrically coupled to the first metallization layer, wherein the inactive side of the substrate includes a divot exposing a portion of the second metallization layer for providing an external electrical connection; a metal bump protruding away from the active side, directly aligned with the divot, and electrically coupled to the first metallization layer; a dielectric layer formed at the inactive side of the substrate, the dielectric layer having a dielectric opening within the divot and over the exposed portion of the second metallization layer; and a barrier layer disposed between the dielectric layer and the second metallization layer, the barrier layer including a barrier opening over the exposed portion of the second metallization layer. ### Claim 9 (depends on 1) The semiconductor device package of claim 1, wherein the metal bump includes an indium metal bump. ### Claim 10 (depends on 8) The semiconductor device package of claim 8, wherein the barrier layer includes tantalum. ### Claim 11 (depends on 1) The semiconductor device package of claim 1, wherein the first metallization layer includes aluminum. ### Claim 12 (depends on 1) The semiconductor device package of claim 1, wherein the second metallization layer includes copper. ### Claim 13 (depends on 1) The semiconductor device package of claim 1, further comprising a third metallization layer positioned between and electrically coupled to the first and second metallization layers. ### Claim 14 (depends on 13) The semiconductor device package of claim 13, wherein the third metallization layer includes copper. ### Claim 15 A semiconductor device package assembly, comprising: a base substrate having a first side and a second side opposite the first side, the base substrate having a first set of metallization layers at the first side, the first set of metallization layers having a contacting area; and at least one semiconductor device package stacked on the base substrate, each of the at least one semiconductor device package having an active side and an inactive side, a second set of metallization layers at the active side, wherein a portion of the second set of metallization layers is exposed through a divot in the inactive side, and the second set of metallization layers is electrically coupled directly to the first set of metallization layers and without using a through-silicon via (TSV), a metal bump in the divot and electrically coupled to the second set of metallization layers, wherein the metal bump is electrically coupled to the first set of metallization layers at the contacting area; and wherein the at least one semiconductor device package has a depth not more than 30 μm. ### Claim 16 (depends on 15) The semiconductor device package assembly of claim 15, wherein the depth is not more than 20 μm. ### Claim 17 (depends on 15) The semiconductor device package assembly of claim 15, wherein the at least one semiconductor device package is a first semiconductor device package, and wherein the metal bump is a first metal bump, and wherein the divot of the first semiconductor device package is configured to receive a second metal bump of a second semiconductor device package such that the second metal bump electrically couples to the second set of metallization layers of the first semiconductor device package without using a TSV. ### Claim 18 A method of manufacturing a semiconductor device package, comprising: forming a semiconductor substrate having an active side and an inactive portion opposite the active side; forming first and second metallization layers in the substrate at the active side, the first and second metallization layers being separated across at least a portion of a thickness of the semiconductor substrate and electrically coupled to each other without using a through-silicon via (TSV); forming a metal bump electrically coupled to the first metallization layer; and thinning the semiconductor substrate to a depth not more than 30 μm based on removing a portion of the inactive portion; forming a divot at a surface of the remaining inactive portion of the substrate, the divot being directly aligned with the metal bump; and exposing a portion of the second metallization layer through the divot, wherein the exposed portion is configured to provide a direct electrical connection to an external circuit. ### Claim 19 (depends on 18) The method of claim 18, wherein the semiconductor device package is a first semiconductor device package, and wherein the metal bump is a first metal bump, and wherein the method further comprises: positioning a second metal bump of a second semiconductor device package in the divot such that the second metal bump electrically couples to the first and second metallization layers of the first semiconductor device package without using a TSV.