# US 11,309,283 B2 · Packaging structure and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,283 B2 - Document ID: US11309283B2 - Status: Granted - Kind: B2 - Application number: 17/099,801 - Filed: 2020-11-17 - Published: 2021-07-01 - Granted: 2022-04-19 - Earliest claimed: 2019-12-31 - Assignees: Powertech Technology Inc. - Applicants: Powertech Technology Inc. - Inventors: Shang-Yu Chang Chien; Nan-Chun Lin; Hung-Hsin Hsu - Web page: https://patentgrep.com/patent/US11309283B2 ## CPC - H10P 72/74: {using temporarily an auxiliary support} - H10W 90/00: Package configurations - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 40/10: Arrangements for heating - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/611: {for connecting multiple chips together} - H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers} - H10W 70/635: {Through-vias} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10P 72/7416: {used during dicing or grinding} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers} - H10P 72/7432: {used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate} - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 72/00: Interconnections or connectors in packages - H10W 72/07254: {changes in dispositions} - H10W 72/247: {Dispositions of multiple bumps} - H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A packaging structure includes a bridge die, a through silicon via die, a first encapsulant, a first active die, a second active die, a second encapsulant, and a redistribution circuit structure. The first encapsulant covers the through silicon via die and the bridge die. The first active die is electrically connected to the bridge die and the through silicon via die. The second active die is electrically connected to the bridge die. The second encapsulant covers the first active die and the second active die. The redistribution circuit structure is electrically connected to the through silicon via die. The through silicon via die is disposed between the first active die and the redistribution circuit structure. A manufacturing method of a packaging structure is also provided. ## Claims ### Claim 1 A packaging structure, comprising: a bridge die; a through silicon via die, comprising a first the through silicon via die, wherein the first the through silicon via die comprises a plurality of first through silicon conductors and a plurality of second through silicon conductors; a first encapsulant, covering the through silicon via die and the bridge die; a first active die, electrically connected to the bridge die and the through silicon via die; a second active die, electrically connected to the bridge die; a passive device, electrically connected to the first the through silicon via die; a second encapsulant, covering the first active di; the second active die and the passive device; and a redistribution circuit structure, electrically connected to the through silicon via die, wherein: the through silicon via die is disposed between the first active die and the redistribution circuit structure; the plurality of first through silicon conductors are overlapped on the first active die, and a first spacing exists between the plurality of first through silicon conductors; the plurality of second through silicon conductors are overlapped on the passive device, and a second spacing exists between the plurality of second through silicon conductors; and the second spacing is greater than or equal to the first spacing. ### Claim 2 (depends on 1) The packaging structure according to claim 1, wherein: the first active die comprises a first active surface; the second active die comprises a second active surface; the through silicon via die comprises a first connection surface and a second connection surface opposite to the first connection surface; the bridge die comprises a bridge connection surface and a bridge back surface opposite to the bridge connection surface; the bridge connection surface faces the first active surface and the second active surface; the first connection surface faces the first active surface; and the redistribution circuit structure is at least disposed on the second connection surface. ### Claim 3 (depends on 2) The packaging structure according to claim 2, wherein: the first encapsulant comprises a first encapsulation surface and a second encapsulation surface opposite to the first encapsulation surface; the first encapsulation surface faces the second encapsulant; and the second connection surface, the bridge back surface, and the second encapsulation surface are substantially coplanar. ### Claim 4 (depends on 3) The packaging structure according to claim 3, wherein the through silicon via die comprises: a silicon substrate; and a through silicon conductor, penetrating the silicon substrate, and comprising a conductive core layer and an insulating shell layer laterally coating the conductive core layer, wherein a partial surface of the silicon substrate, a partial surface of the conductive core layer, and a partial surface of the insulating shell layer are substantially coplanar and construct at least one part of the second connection surface. ### Claim 5 (depends on 2) The packaging structure according to claim 2, wherein the through silicon via die comprises: a silicon substrate; a through silicon conductor, penetrating the silicon substrate, and comprising a conductive core layer and an insulating shell layer laterally coating the conductive core layer; and; a connection pad, disposed on the silicon substrate and comprising a conductive connection layer, wherein the conductive core layer and the conductive connection layer are same films. ### Claim 6 (depends on 1) The packaging structure according to claim 1, wherein the bridge die comprises: a silicon substrate; and an interconnection structure, disposed on the silicon substrate, and comprising a plurality of conductive layers and an insulating layer clamped between the plurality of conductive layers. ### Claim 7 (depends on 1) The packaging structure according to claim 1, wherein the bridge die is disposed between the second active die and the redistribution circuit structure. ### Claim 8 (depends on 1) The packaging structure according to claim 1, wherein the first encapsulant and the second encapsulant physically contact. ### Claim 9 (depends on 1) The packaging structure according to claim 1, further comprising: a heat dissipation member, at least thermally coupled to the first active die or the second active die. ### Claim 10 A manufacturing method of a packaging structure, comprising: providing a through silicon via die and a bridge die, wherein the through silicon via die comprises a first the through silicon via die, and the first the through silicon via die comprises a plurality of first through silicon conductors and a plurality of second through silicon conductors; forming a first encapsulant covering the through silicon via die and the bridge die; forming a redistribution circuit structure electrically connected to the through silicon via die; configuring a first active die electrically connected to the bridge die and the through silicon via die; configuring a second active die electrically connected to the bridge die; configuring a passive device electrically connected to the first the through silicon via die; and forming a second encapsulant covering the first active die, the second active die, and the passive device, wherein after the step of forming the redistribution circuit structure and the step of configuring the first active die, the through silicon via die is disposed between the first active die and the redistribution circuit structure, wherein after the step of configuring the first active die and the step of configuring a passive device electrically connected to the first the through silicon via die, the plurality of first through silicon conductors are overlapped on the first active die and the plurality of second through silicon conductors are overlapped on the passive device, wherein a first spacing exists between the plurality of first through silicon conductors, a second spacing exists between the plurality of second through silicon conductors and the second spacing is greater than or equal to the first spacing. ### Claim 11 (depends on 10) The manufacturing method of the packaging structure according to claim 10, wherein: the step of providing the through silicon via die and the bridge die comprises configuring the through silicon via die and the bridge die on a first carrier board; and the step of forming the first encapsulant comprises forming the first encapsulant on the carrier board, and removing the first carrier board before configuring the first active die or the second active die. ### Claim 12 (depends on 10) The manufacturing method of the packaging structure according to claim 10, further comprising: before configuring the first active die or the second active die, placing the through silicon via die, the bridge die, the first encapsulant, and the redistribution circuit structure on a second carrier board, and at least locating the redistribution circuit structure between the through silicon via die and the second carrier board; after forming the second encapsulant, removing the second carrier board. ### Claim 13 (depends on 10) The manufacturing method of the packaging structure according to claim 10, wherein the step of forming the first encapsulant comprises: forming a first encapsulation material to cover the through silicon via die and the bridge die; and performing a first thinning process, to remove a part of the first encapsulation material, to form a first encapsulant laterally covering the through silicon via die and the bridge die, and expose the through silicon via die and the bridge die. ### Claim 14 (depends on 10) The manufacturing method of the packaging structure according to claim 10, wherein the step of forming the second encapsulant comprises: forming a second encapsulation material to cover the first active die, the second active die and the passive device; and performing a second thinning process, to remove a part of the second encapsulation material, to form a second encapsulant laterally covering the first active die and the second active die, and expose the first active die and the second active die.