# US 11,309,281 B2 · Overlapping die stacks for NAND package architecture

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- Number: US 11,309,281 B2
- Document ID: US11309281B2
- Status: Granted
- Kind: B2
- Application number: 17/003,789
- Filed: 2020-08-26
- Published: 2022-03-03
- Granted: 2022-04-19
- Earliest claimed: 2020-08-26
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Enyong Tai; Hem P. Takiar; Li Wang; Hong Wan Ng
- Web page: https://patentgrep.com/patent/US11309281B2

## CPC

- H10W 90/00: Package configurations
- H10W 72/075: {of bond wires}
- H10W 72/50: Bond wires
- H10W 72/073: {of die-attach connectors}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/295: {optical coupling}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device assembly includes a substrate having a plurality of external connections, a first stack of semiconductor dies disposed directly over a first location on the substrate and electrically coupled to a first subset of the plurality of external connections, and a second stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. A portion of the semiconductor dies of the second stack overlaps a portion of the semiconductor dies of the first stack. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first stack and the second stack.

## Claims

### Claim 1

A semiconductor assembly, comprising:
a substrate including external connections;
a first stack of semiconductor dies disposed directly over a first location on the substrate and having a first height and the first stack electrically coupled to a first subset of the external connections;
a second stack of semiconductor dies disposed directly over a second location on the substrate and having a second height different than the first height and the second stack electrically coupled to a second subset of the external connections; and
an encapsulant at least partially encapsulating the substrate, the first stack and the second stack,
wherein the first stack includes an uppermost semiconductor die of the first stack, the second stack includes an uppermost semiconductor dies of the second stack, and at least a portion of the uppermost semiconductor die of the second stack is superimposed above at least a portion of the uppermost semiconductor die of the first stack.

### Claim 2 (depends on 1)

The semiconductor assembly of claim 1, further comprising a spacer disposed underneath a lowermost semiconductor die of the first stack or second stack.

### Claim 3 (depends on 2)

The semiconductor assembly of claim 2 wherein the spacer is a dielectric spacer.

### Claim 4 (depends on 2)

The semiconductor assembly of claim 2 wherein the spacer is a controller die or a logic die.

### Claim 5 (depends on 1)

The semiconductor assembly of claim 1 wherein:
each semiconductor die of the first stack includes a first die thickness; and
each semiconductor die of the second stack includes a second die thickness different than the first die thickness.

### Claim 6 (depends on 1)

The semiconductor assembly of claim 1, further comprising:
a first die attach film disposed between each semiconductor die in the first stack and having a first die attach film thickness; and
a second die attach film disposed between each semiconductor die in the second stack and having a second die attach film thickness different than the first die attach film thickness.

### Claim 7 (depends on 1)

The semiconductor assembly of claim 1, further comprising a controller die disposed on the substrate between the first stack and second stack.

### Claim 8 (depends on 1)

The semiconductor assembly of claim 1 wherein the first stack and the second stack include a same number of semiconductor dies.

### Claim 9 (depends on 1)

The semiconductor assembly of claim 1 wherein:
the first stack includes a lowermost semiconductor die of the first stack and at least one upper semiconductor die stacked over the lowermost semiconductor die of the first stack; and
each upper semiconductor die of the first stack is offset from a semiconductor die directly below by a first offset in a first direction.

### Claim 10 (depends on 9)

The semiconductor assembly of claim 9 wherein:
the second stack includes a lowermost semiconductor die of the second stack and at least one upper semiconductor die stacked over the lowermost semiconductor die of the second stack; and
each upper semiconductor die of the second stack is offset from a semiconductor die directly below by a second offset in a second direction.

### Claim 11 (depends on 10)

The semiconductor assembly of claim 10 wherein the first offset is substantially equal to the second offset.

### Claim 12 (depends on 10)

The semiconductor assembly of claim 10 wherein the first direction is substantially opposite to the second direction.

### Claim 13 (depends on 1)

The semiconductor assembly of claim 1 wherein:
the first stack of semiconductor dies is electrically connected to the first subset of the external connections by a first plurality of wirebonds; and
the second stack of semiconductor dies is electrically connected to the second subset of the external connections by a second plurality of wirebonds.

### Claim 14 (depends on 13)

The semiconductor assembly of claim 13 wherein:
the substrate includes a first plurality of bond pads corresponding to the first stack and a second plurality of bond pads corresponding to the second stack;
each of the first plurality of bond pads is directly coupled to only one of the first plurality of wirebonds; and
each of the second plurality of bond pads is directly coupled to only one of the second plurality of wirebonds.

### Claim 15 (depends on 1)

The semiconductor assembly of claim 1 wherein a distance between a lowermost semiconductor die of the first stack and a lowermost semiconductor die of the second stack is in the range of 50 to 100 microns.

### Claim 16

A method of manufacturing a semiconductor assembly, the method comprising:
providing a substrate including external connections;
stacking, directly over a first location on the substrate, a first plurality of semiconductor dies on the substrate in a first stack having a first height;
stacking, directly over a second location on the substrate, a second plurality of semiconductor dies on the substrate in a second stack having a second height different than the first height;
wirebonding, subsequent to stacking the first and second stacks, the first and second pluralities of semiconductor dies to a first subset of the external connections and a second subset of the external connections, respectively; and
providing an encapsulant to at least partially encapsulate the substrate, the first stack and the second stack,
wherein the first stack includes an uppermost semiconductor die of the first stack, the second stack includes an uppermost semiconductor dies of the second stack, and at least a portion of the uppermost semiconductor die of the second stack is superimposed above at least a portion of the uppermost semiconductor die of the first stack.

### Claim 17 (depends on 16)

The method of claim 16 wherein the wirebonding is performed in a single operation uninterrupted by any stacking.

### Claim 18 (depends on 17)

The method of claim 17, further comprising disposing a spacer at the second location on the substrate.

### Claim 19

A method of manufacturing a semiconductor assembly, the method comprising:
providing a substrate including external connections;
stacking, directly over a first location on the substrate, a first plurality of semiconductor dies on the substrate in a first stack;
disposing, directly over a second location on the substrate, a spacer on the substrate in a second stack;
stacking a second plurality of semiconductor dies on the spacer in the second stack;
wirebonding, subsequent to stacking the first and second stacks, the first and second pluralities of semiconductor dies to a first subset of the external connections and a second subset of the external connections, respectively; and
providing an encapsulant to at least partially encapsulate the substrate, the first stack and the second stack,
wherein the first stack includes an uppermost semiconductor die of the first stack, the second stack includes an uppermost semiconductor dies of the second stack, and at least a portion of the uppermost semiconductor die of the second stack is superimposed above at least a portion of the uppermost semiconductor die of the first stack.