# US 11,309,280 B2 · Semiconductor device package

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- Number: US 11,309,280 B2
- Document ID: US11309280B2
- Status: Granted
- Kind: B2
- Application number: 16/923,418
- Filed: 2020-07-08
- Published: 2020-10-29
- Granted: 2022-04-19
- Earliest claimed: 2017-11-16
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Yong-hoon Kim; Kil-soo Kim; Kyung-suk Oh; Tae-joo Hwang
- Web page: https://patentgrep.com/patent/US11309280B2

## CPC

- H10W 90/00: Package configurations
- H04M 1/0277: {for a printed circuit board assembly}
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 40/73: for cooling by change of state
- H10W 42/271: {the arrangements being between stacked chips}
- H10W 90/20: Configurations of stacked chips
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H04M: TELEPHONIC COMMUNICATION (circuits for controlling other apparatus via a telephone cable and not involving telephone switching apparatus G08)

## Abstract

An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.

## Claims

### Claim 1

A semiconductor device package, comprising:
a redistribution layer;
a logic chip on the redistribution layer;
a stack of memory chips next to the logic chip on the redistribution layer, the memory chips are stacked in a vertical direction and connected to one another through through-silicon vias (TSVs); and
a molding surrounding a sidewall of the logic chip and a sidewall of the stack of memory chips, wherein:
a thickness of the logic chip in the vertical direction is greater than a thickness of the stack of memory chips in the vertical direction,
the molding does not cover a top surface of the logic chip,
the molding covers a top surface of an uppermost memory chip of the stack of memory chips, and
no semiconductor chip is located on the top surface of the uppermost memory chip.

### Claim 2 (depends on 1)

The semiconductor device package as claimed in claim 1, wherein the logic chip comprises an application processor chip.

### Claim 3 (depends on 1)

The semiconductor device package as claimed in claim 1, wherein each of the memory chips comprises a DRAM chip.

### Claim 4 (depends on 1)

The semiconductor device package as claimed in claim 1, wherein no semiconductor chip is located on the top surface of the logic chip.

### Claim 5 (depends on 1)

The semiconductor device package as claimed in claim 1, wherein the molding directly contacts with the logic chip.

### Claim 6 (depends on 1)

The semiconductor device package as claimed in claim 1, wherein a thermal conductivity of the molding is lower than a thermal conductivity of the logic chip.

### Claim 7 (depends on 1)

The semiconductor device package as claimed in claim 1, wherein an amount of heat generated by the logic chip is greater than an amount of heat generated by the stack of memory chips.

### Claim 8

An electronic device, comprising:
a redistribution layer;
a logic chip on the redistribution layer;
a stack of memory chips next to the logic chip on the redistribution layer, the memory chips are stacked in a vertical direction and connected to one another through through-silicon vias (TSVs); and
a molding surrounding a sidewall of the logic chip and a sidewall of the stack of memory chips;
a heat dissipation structure on a top surface of the logic chip; and
a thermal interface material (TIM) layer between the top surface of the logic chip and the heat dissipation structure, wherein:
the molding does not cover the top surface of the logic chip, and the TIM layer covers the top surface of the logic chip,
the molding does not cover a top surface of an uppermost memory chip of the stack of memory chips, and the TIM layer does not extend over the top surface of the uppermost memory chip,
no semiconductor chip is located on the top surface of the uppermost memory chip,
no semiconductor chip is located on the top surface of the logic chip, and
no semiconductor chip is located between the logic chip and the redistribution layer.

### Claim 9 (depends on 8)

The electronic device as claimed in claim 8, wherein a thickness of the logic chip in the vertical direction is the same as a thickness of the stack of memory chips in the vertical direction.

### Claim 10 (depends on 8)

The electronic device as claimed in claim 8, wherein the top surface of the uppermost memory chip, the top surface of the logic chip, and a top surface of the molding are coplanar.

### Claim 11 (depends on 8)

The electronic device as claimed in claim 8, wherein the TIM layer does not contact with the top surface of the uppermost memory chip.

### Claim 12 (depends on 11)

The electronic device as claimed in claim 11, wherein the top surface of the uppermost memory chip is spaced apart from the heat dissipation structure.

### Claim 13 (depends on 8)

The electronic device as claimed in claim 8, wherein a maximum length of the heat dissipation structure in a horizontal direction perpendicular to the vertical direction is greater than a maximum length of the redistribution layer in the horizontal direction.

### Claim 14 (depends on 8)

The electronic device as claimed in claim 8, wherein a maximum length of the heat dissipation structure in a horizontal direction perpendicular to the vertical direction is greater than a maximum length of the molding in the horizontal direction, and
the heat dissipation structure extends in the horizontal direction beyond outermost sidewalls of the molding so that the outermost sidewalls of the molding do not contact the heat dissipation structure in the horizontal direction.

### Claim 15

An electronic device, comprising:
a redistribution layer;
an application processor chip on the redistribution layer;
a stack of DRAM chips next to the application processor chip on the redistribution layer, the DRAM chips are connected to one another through through-silicon vias (TSVs);
a molding extending in a vertical direction along a sidewall of the application processor chip and along a sidewall of the stack of DRAM chips; and
a heat dissipation structure on a top surface of the application processor chip, wherein:
a top surface of the molding, the top surface of the application processor chip, and a top surface of an uppermost DRAM chip of the stack of DRAM chips are coplanar,
no semiconductor chip is located on the top surface of the uppermost DRAM chip, and
the heat dissipation structure extends, in a horizontal direction perpendicular to the vertical direction, beyond outermost sidewalls of the molding so that the outermost sidewalls of the molding do not contact the heat dissipation structure in the horizontal direction.