# US 11,309,279 B2 · Package structure of wafer-level system-in-package

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- Number: US 11,309,279 B2
- Document ID: US11309279B2
- Status: Granted
- Kind: B2
- Application number: 17/078,944
- Filed: 2020-10-23
- Published: 2021-02-11
- Granted: 2022-04-19
- Earliest claimed: 2018-05-03
- Assignees: Ningbo Semiconductor International Corporation
- Applicants: Ningbo Semiconductor International Corporation
- Inventors: Mengbin Liu; Hailong Luo
- Web page: https://patentgrep.com/patent/US11309279B2

## CPC

- H10W 72/0198: {batch processes}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 72/073: {of die-attach connectors}
- H10W 74/014: {using batch processing}
- H10W 74/016: {using moulds}
- H10W 90/00: Package configurations
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/013: {of die-attach connectors}
- H10W 72/019: {of bond pads}
- H10W 72/07352: {changes in structures or sizes}
- H10W 72/321: {Structures or relative sizes of die-attach connectors}
- H10W 72/331: {Shapes of die-attach connectors}
- H10W 72/354: {comprising polymers}
- H10W 72/874: {On different surfaces}
- H10W 72/90: Bond pads, in general
- H10W 72/9413: {on encapsulations}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/732: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A wafer-level system-in-package (WLSiP) package structure is provided. The WLSiP package structure includes a device wafer, an adhesive layer, and a plurality of second chips. The device wafer includes a first front surface having a plurality of first chips integrated therein and a first back surface opposing the first front surface. The adhesive layer is formed on the first front surface of the device wafer and the adhesive layer includes a plurality of through-holes exposing the first front surface. The plurality of second chips are bonded to the device wafer, and the plurality of second chips are bonded with the adhesive layer to cover the plurality of first through-holes in a one-to-one correspondence.

## Claims

### Claim 1

A wafer-level system-in-package (WLSiP) package structure, comprising:
a device wafer, wherein the device wafer includes a first front surface having a plurality of first chips integrated therein and a first back surface opposing the first front surface;
an adhesive layer, formed on the first front surface of the device wafer, wherein the adhesive layer includes a plurality of through-holes exposing the first front surface; and
a plurality of second chips, bonded to the device wafer, wherein the plurality of second chips are bonded with the adhesive layer to cover the plurality of first through-holes in a one-to-one correspondence.

### Claim 2 (depends on 1)

The package structure according to claim 1, wherein:
the second chip includes a second front surface having semiconductor devices formed thereon and a second back surface opposing the second front surface; and
one of the second front surface and the second back surface is bonded with the adhesive layer.

### Claim 3 (depends on 1)

The package structure according to claim 1, wherein:
the adhesive layer is made of one of a dry film, polyimide, polybenzoxazole, and benzocyclobutene.

### Claim 4 (depends on 1)

The package structure according to claim 1, wherein:
the adhesive layer exposes the first front surface at a location corresponding to the through-hole; or
the adhesive layer covers the first front surface at a location corresponding to the second chip.

### Claim 5 (depends on 1)

The package structure according to claim 1, wherein:
the plurality of second chips have at least one type of function.