# US 11,309,277 B2 · Chip assembling on adhesion layer or dielectric layer, extending beyond chip, on substrate

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- Number: US 11,309,277 B2
- Document ID: US11309277B2
- Status: Granted
- Kind: B2
- Application number: 16/904,052
- Filed: 2020-06-17
- Published: 2020-10-08
- Granted: 2022-04-19
- Earliest claimed: 2015-02-04
- Assignees: Infineon Technologies AG
- Applicants: Infineon Technologies AG
- Inventors: Petteri Palm; Thorsten Scharf; Ralf Wombacher
- Web page: https://patentgrep.com/patent/US11309277B2

## CPC

- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/095: {of vias therein}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 76/153: having interconnections in passages through the insulating or insulated base
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/07323: {Active alignment, e.g. using optical alignment using marks or sensors}
- H10W 72/874: {On different surfaces}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/9413: {on encapsulations}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Electronic module, which comprises a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer, wherein the first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.

## Claims

### Claim 1

A method of manufacturing at least one electronic module, the method comprising:
applying a first adhesion layer at least to an entire component mounting area of a conductive first substrate;
direct or indirect mounting of a first main surface of at least one electronic chip on a partial region of the first adhesion layer;
applying a second adhesion layer on a conductive second substrate;
direct or indirect mounting of a second main surface of the at least one electronic chip on a respective partial region of the second adhesion layer;
electrical contacting of the at least one electronic chip through the first adhesion layer;
converting the first adhesion layer to a dielectric layer; and
singularizing of a plurality of electronic chips between the first substrate and the second substrate to a plurality of electronic modules, wherein each electronic module comprises at least a section of the first substrate, a section of the first adhesion layer wherein edges of the first adhesion layer are exposed, a section of the second substrate, and at least one electronic chip.

### Claim 2 (depends on 1)

The method of claim 1, where converting the first adhesion layer to a dielectric layer includes hardening the first adhesion layer.

### Claim 3 (depends on 2)

The method of claim 2, where hardening the first adhesion layer includes hardening a polymer adhesion layer.

### Claim 4 (depends on 1)

The method of claim 1, where applying the first adhesion layer comprises:
forming a first partial layer;
converting the first partial layer to a dielectric; and
forming a second partial layer on the first partial layer.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
converting the second adhesion layer to a dielectric layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the second adhesion layer is applied at least to an entire component mounting area of the second substrate.

### Claim 7 (depends on 5)

The method of claim 5, wherein at least one of the first adhesion layer and of the second adhesion layer is applied completely on the respective substrate.

### Claim 8 (depends on 5)

The method of claim 5, wherein at least one through hole for electrically contacting the respective main surface of the respective electronic chip is formed in at least one of the first adhesion layer and of the second adhesion layer, and is filled at least partially with an electrically conductive material.

### Claim 9 (depends on 1)

The method of claim 1, wherein at least one of the first substrate and the second substrate is structured to form electrically conductive paths.

### Claim 10 (depends on 9)

The method of claim 9, wherein at least one of the first substrate and the second substrate is structured to form electrically conductive paths.

### Claim 11 (depends on 9)

The method of claim 9, wherein the first adhesion layer has a constant thickness throughout, except of the region where an electrical contacting is arranged.

### Claim 12 (depends on 1)

The method of claim 1, wherein the first adhesion layer has a constant thickness throughout, except of the region where an electrical contacting is arranged.

### Claim 13

A method for manufacturing at least one electronic module, the method comprising:
applying a first adhesion layer at least to an entire component mounting area of a conductive first substrate;
direct or indirect mounting of a first main surface of a plurality of electronic chips on a respective partial region of the first adhesion layer;
applying a second adhesion layer on a conductive second substrate;
direct or indirect mounting of a second main surface of the plurality of electronic chips on a respective partial region of the second adhesion layer;
converting at least one of the first adhesion layer and the second adhesion layer to a dielectric layer; and
singularizing of the plurality of electronic chips between the first substrate and the second substrate to a plurality of electronic modules, wherein each electronic module comprises at least a section of the first substrate, a section of the first adhesion layer wherein edges of the first adhesion layer are exposed, a section of the second adhesion layer wherein edges of the second adhesion layer are exposed, a section of the second substrate, and at least one electronic chip.

### Claim 14 (depends on 13)

The method of claim 13, wherein at least one of the first adhesion layer and the second adhesion layer is applied essentially completely on the respective substrate, and wherein at least one through hole for electrically contacting the respective main surface of the respective electronic chip is formed in at least one of the first adhesion layer and the second adhesion layer, and is filled at least partially with an electrically conductive material.

### Claim 15 (depends on 13)

The method of claim 13, where converting at least one of the first adhesion layer and the second adhesion layer to a dielectric layer includes hardening the first adhesion layer and hardening the second adhesion layer.

### Claim 16 (depends on 13)

The method of claim 13, wherein at least one of the first adhesion layer and the second adhesion layer is formed of a first partial layer and a second partial layer, including converting the first partial layer to a first partial dielectric layer, forming the second partial layer on the first partial layer, and converting the second partial layer to a second partial dielectric layer.

### Claim 17

A method for manufacturing at least one electronic module, the method comprising:
applying a first adhesion layer at least to an entire component mounting area of a conductive first substrate, wherein the first adhesion layer has a constant thickness throughout, except of the region where an electrical contacting is arranged;
direct or indirect mounting of a first main surface of a plurality of electronic chips on a respective partial region of the first adhesion layer;
applying a second adhesion layer on a conductive second substrate, wherein the second adhesion layer has a constant thickness throughout, except of the region where an electrical contacting is arranged;
converting the first adhesion layer and the second adhesion layer to dielectric layers; and
direct or indirect mounting of a second main surface of the plurality of electronic chips on a respective partial region of the second adhesion layer.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
singularizing of the plurality of electronic chips between the first substrate and the second substrate to a plurality of electronic modules, wherein each electronic module comprises at least a section of the first substrate, a section of the first adhesion layer wherein edges of the first adhesion layer are exposed, a section of the second adhesion layer wherein edges of the second adhesion layer are exposed, a section of the second substrate, and at least one electronic chip.

### Claim 19 (depends on 17)

The method of claim 17, comprising converting the first adhesion layer to a first dielectric layer at a time different than when converting the second adhesion layer to a second dielectric layer.

### Claim 20 (depends on 17)

The method of claim 17, where the first adhesion layer has multiple layers.