# US 11,309,271 B2 · Chip structure and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,271 B2 - Document ID: US11309271B2 - Status: Granted - Kind: B2 - Application number: 16/941,486 - Filed: 2020-07-28 - Published: 2021-02-04 - Granted: 2022-04-19 - Earliest claimed: 2019-07-29 - Assignees: Xintec Inc. - Applicants: Xintec Inc. - Inventors: Jiun-Yen Lai; Chia-Hsiang Chen - Web page: https://patentgrep.com/patent/US11309271B2 ## CPC - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 72/013: {of die-attach connectors} - H10W 20/0245: {comprising use of blind vias during the manufacture} - H10W 20/0253: {comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/90: Bond pads, in general - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/6528: {of the portions that connect to chips, wafers or package parts} - H10W 72/0198: {batch processes} - H10W 72/073: {of die-attach connectors} - H10W 72/344: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL - H10W 90/732: {between stacked chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion extends from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via. ## Claims ### Claim 1 A chip structure, comprising: a first substrate having a first inclined sidewall; a second substrate located on a lower surface of the first substrate, and having an upper portion and a lower portion, wherein the lower portion extends from the upper portion, and the upper portion is between the first substrate and the lower portion and has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall; a conductive via in the lower portion; a redistribution layer extending from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and electrically connected to the conductive via; and a bonding layer between the first substrate and the second substrate, wherein the first substrate, the second substrate, and the bonding layer define a cavity. ### Claim 2 (depends on 1) The chip structure of claim 1, wherein a lateral surface of the bonding layer is in contact with the redistribution layer. ### Claim 3 (depends on 1) The chip structure of claim 1, wherein the bonding layer has an inclined lateral surface, and the chip structure further comprises: an isolation layer located between the conductive via and the second substrate, on a lower surface of the second substrate, between the redistribution layer and the first substrate, on the top surface of the first substrate, on the first inclined sidewall, on the inclined lateral surface of the bonding layer, and on the second inclined sidewall. ### Claim 4 (depends on 1) The chip structure of claim 1, wherein the bonding layer has an inclined lateral surface, and the chip structure further comprises: a surface protecting layer located on the top surface of the first substrate, the redistribution layer, the first inclined lateral sidewall, the inclined lateral surface of the bonding layer, the second inclined sidewall, and the lower portion of the second substrate. ### Claim 5 (depends on 1) The chip structure of claim 1, wherein the first substrate has a conductive pad, and a sidewall of the conductive pad is in contact with the redistribution layer. ### Claim 6 (depends on 5) The chip structure of claim 5, wherein the conductive pad of the first substrate is located on the bonding layer. ### Claim 7 (depends on 1) The chip structure of claim 1, wherein the second substrate has a conductive pad, and a sidewall of the conductive pad is in contact with the redistribution layer. ### Claim 8 (depends on 7) The chip structure of claim 7, wherein the bonding pad is located on the conductive pad of the second substrate. ### Claim 9 (depends on 1) The chip structure of claim 1, wherein each of the first substrate and the second substrate has a conductive pad, and the bonding layer located among the two conductive pads and the redistribution layer. ### Claim 10 (depends on 1) The chip structure of claim 1, wherein the redistribution layer is stepped. ### Claim 11 (depends on 1) The chip structure of claim 1, wherein the redistribution layer has two horizontal portions and an inclined portion, and two ends of the inclined portion are respectively connected to the two horizontal portions. ### Claim 12 (depends on 11) The chip structure of claim 11, wherein the two horizontal portions of the redistribution layer are respectively located on the top surface of the first substrate and the top surface of the lower portion, and the inclined portion is located on the first inclined sidewall and the second inclined sidewall. ### Claim 13 (depends on 11) The chip structure of claim 11, wherein the horizontal portion located on the top surface of the lower portion is in contact with a top surface of the conductive via. ### Claim 14 A manufacturing method of a chip structure, comprising: bonding, by a bonding layer, a lower surface of a first substrate to a second substrate such that the bonding layer is between the first substrate and the second substrate, and the first substrate, the second substrate, and the bonding layer define a cavity; forming an opening in the second substrate; forming a conductive via in the opening of the second substrate; forming a trench in the first substrate and the second substrate such that the conductive via is exposed through the trench, wherein the first substrate has a first inclined sidewall, and the second substrate has an upper portion and a lower portion, wherein the lower portion extends from the upper portion, and the upper portion is between the first substrate and the lower portion and has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall; and forming a redistribution layer that extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via. ### Claim 15 (depends on 14) The manufacturing method of the chip structure of claim 14, wherein the conductive via is formed by electroplating or electroless plating. ### Claim 16 (depends on 14) The manufacturing method of the chip structure of claim 14, further comprising: after forming the conductive via, bonding the second substrate to a carrier. ### Claim 17 (depends on 16) The manufacturing method of the chip structure of claim 16, further comprising: after forming the redistribution layer, removing the carrier from the second substrate. ### Claim 18 (depends on 14) The manufacturing method of the chip structure of claim 14, wherein the trench is formed by cutting the first substrate and the second substrate with a cutting tool. ### Claim 19 (depends on 14) The manufacturing method of the chip structure of claim 14, further comprising: after forming the redistribution layer, cutting the second substrate along the trench, wherein a shape of a sidewall of the second substrate is upright or stepped based on a cutting depth of the second substrate. ### Claim 20 A chip structure, comprising: a first substrate having a first inclined sidewall; a second substrate located on a lower surface of the first substrate, and having an upper portion and a lower portion, wherein the lower portion extends from the upper portion, and the upper portion is between the first substrate and the lower portion and has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall; a conductive via in the lower portion; and a redistribution layer extending from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and electrically connected to the conductive via, wherein the second substrate has a conductive pad, and a sidewall of the conductive pad is in contact with the redistribution layer. ### Claim 21 (depends on 20) The chip structure of claim 20, further comprising: a bonding layer located between the first substrate and the second substrate, and located on the conductive pad of the second substrate.